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ADC12QS065 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC12QS065
Beschreibung Quad 12-Bit 65 MSPS A/D Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 18 Seiten
ADC12QS065 Datasheet, Funktion
PRELIMINARY
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ADC12QS065
Quad 12-Bit 65 MSPS A/D Converter with LVDS
Serialized Outputs
General Description
This is Preliminary Information for a product currently in
development. ALL specifications are design targets and
are subject to change.
The ADC12QS065 is a low power, high performance CMOS
4-channel analog-to-digital converter with LVDS serialized
outputs. The ADC12QS065 digitizes signals to 12 bits reso-
lution at sampling rates up to 65 MSPS while consuming a
typical 200 mW/ADC from a single 3.0V supply. Sampled
data is transformed into high speed serial LVDS output data
streams. Clock and frame LVDS pairs aid in data capture.
The ADC12QS065’s six differential pairs transmit data over
backplanes or cable and also make PCB design easier. In
addition, the reduced cable, PCB trace count, and connector
size tremendously reduce cost.
No missing codes performance is guaranteed over the full
operating temperature range. The pipeline ADC architecture
achieves >11 Effective Bits over the entire Nyquist band at
65 MSPS.
The ADC12QS065 output pins can be put into a high imped-
ance state. The serializer PLL can lock to frequencies be-
tween 20 MHz and 65 MHz.
When not converting, power consumption can be reduced by
pulling the PD (Power Down) pin high, placing the converter
into a low power state where it typically consumes less than
3 mW total, and from which recovery is less than 5 ms. The
ADC12QS065’s speed, resolution and single supply opera-
tion makes it well suited for a variety of applications in
ultrasound, imaging, video and communications. Operating
over the industrial (-40˚C to +85˚C) temperature range, the
ADC12QS065 is available in a 64 pin TQFP package.
Features
n Single +3.0V supply operation
n Internal sample-and-hold
n Internal reference
n Low power consumption
n Power down mode
n Clock and Data Frame Timing
n 780 Mbps serial LVDS data rate (at 65 MHz clock)
n LVDS serial output rated for 100 Ohm load
Key Specifications
n Resolution
n DNL
n SNR (fIN = 10 MHz)
n SFDR (fIN = 10 MHz)
n ENOB (at Nyquist)
n Power Consumption
n -- Operating, 65 MSPS, per ADC
n -- Power Down Mode
12 Bits
±0.3 LSB (typ)
68.5 dB (typ)
85 dB (typ)
11 Bits (typ)
200 mW (typ)
< 3 mW (typ)
Applications
n Ultrasound
n Medical Imaging
n Communications
n Portable Instrumentation
n Digital Video
Connection Diagram
© 2005 National Semiconductor Corporation DS201068
20106801
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ADC12QS065 Datasheet, Funktion
Converter Electrical Characteristics (Continued)
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NOTE: This product is currently under development. As such, the parameters specified in this section are DESIGN
TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place. Un-
less otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, VA = VD = VDR= +3.0V, VIN =
2VP-P , VREF = +1.0V external, VCOM=1.5V, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin. Boldface limits apply
for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical Limits
(Note 10) (Note 10)
Units
(Limits)
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full Power Bandwidth
0 dBFS Input, Output at −3 dB
300
MHz
SNR
Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
THD
Total Harmonic Distortion
H2 Second Harmonic Distortion
H3 Third Harmonic Distortion
SFDR Spurious Free Dynamic Range
IMD Intermodulation Distortion
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 33 MHz, VIN = −0.5 dBFS
fIN = 9.6 MHz and 10.2 MHz,
each = −6.0 dBFS
68.5
68.5
68.3
68.5
68.3
68
11.1
11.1
11
−83
−83
−77
−90
−90
−83
−85
−85
−80
85
85
80
−70
dBc
dBc (min)
dBc
dBc
dBc (min)
dBc
Bits
Bits (min)
Bits
dBc
dBc (min)
dBc
dBc
dBc (min)
dBc
dBc
dBc (min)
dBc
dBc
dBc (min)
dBc
dBFS
FPBW Full Power Bandwidth
300 MHz
INTER-CHANNEL CHARACTERISTICS
Channel — Channel Offset Match
±0.3
%FS
Channel — Channel Gain Match
±4 %FS
Crosstalk (between any two
10 MHz Tested, Channel;
20 MHz Other Channel
80
dBc
channels)
10 MHz Tested, Channel;
65 MHz Other Channel
80
dBc
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ADC12QS065 pdf, datenblatt
Functional Description
Operating on a single +3.0V supply, the ADC12QS065 uses
a pipeline architecture and has error correction circuitry to
help ensure maximum performance. The differential analog
input signal is digitized to 12 bits. The user has the choice of
using an internal 1.0 Volt or 0.5 Volt stable reference, or
using an external reference. Any external reference is buff-
ered on-chip to ease the task of driving that pin.
Sampled data is transformed into high speed serial output
LVDS data streams. Clock and frame LVDS pairs aid in data
capture. The ADC12QS065’s six differential pairs transmit
data over backplanes or cable and also make PCB design
easier.
The output word rate is the same as the clock frequency,
which can be between 20 MSPS and 65 MSPS (typical) with
fully specified performance at 65 MSPS. The analog input for
all channels are acquired at the rising edge of the clock and
the digital data for a given sample is delayed by the pipeline
for 9 clock cycles.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12QS065:
2.7V VA 3.6V
VD = VA = VDR
20 MHz fCLK 65 MHz
0.8V VREF 1.2V (for an external reference)
0.5V VCM 2.0V
2.0 ANALOG INPUTS
There is one reference input pin, VREF, which is used to
select an internal reference, or to supply an external refer-
ence. The ADC12QS065 has four analog signal input pairs,
VIN 1+ and VIN 1-, VIN 2+ and VIN 2- , VIN 3+ and VIN 3-, VIN
4+ and VIN 4- . Each pair of pins forms a differential input
pair. There are two VREG pins for decoupling the internal
1.8V regulator.
2.1 Reference Pins
The ADC12QS065 is designed to operate with an internal
1.0V or 0.5V reference, or an external 1.0V reference, but
performs well with external reference voltages in the range
of 0.8V to 1.2V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12QS065. Increasing
the reference voltage (and the input signal swing) beyond
1.2V may degrade THD for a full-scale input, especially at
higher input frequencies.
It is important that all grounds associated with the reference
voltage and the analog input signal make connection to the
ground plane at a single, quiet point to minimize the effects
of noise currents in the ground path.
The six Reference Bypass Pins (VREFT12, VREFB12,
VCOM12, VREFT34, VREFB34 and VCOM34) are made
available for bypass purposes. All these pins should each be
bypassed to ground with a 0.1 µF capacitor. A 10 µF capaci-
tor should be placed between the VREFT12 and VREFB12
pins and between the VREFT34 and VREFB34 pins, as
shown in Figure 4. This configuration is necessary to avoid
reference oscillation, which could result in reduced SFDR
and/or SNR.
Smaller capacitor values than those specified will allow
faster recovery from the power dwowwnwm.Doadtea,Sbhuet emt4aUy.rceosmult in
degraded noise performance. DO NOT LOAD these pins.
Loading any of these pins may result in performance degra-
dation.
The nominal voltages for the reference bypass pins are as
follows:
VCOM = 1.5 V
VREFT = VCOM + VREF / 2
VREFB = VCOM − VREF / 2
User choice of an on-chip or external reference voltage is
provided. When INTREF (pin 57) is high, the VREF pin se-
lects the internal reference voltage. The internal 1.0 Volt
reference is in use when the the VREF pin is connected to VA.
When the VREF pin is connected to AGND, the internal 0.5
Volt reference is in use. When INTREF (pin 57) is low, a
voltage in the range of 0.8V to 1.2V is applied to the VREF pin
and that is used for the voltage reference. When an external
reference is used, the VREF pin should be bypassed to
ground with a 0.1 µF capacitor close to the reference input
pin. There is no need to bypass the VREF pin when the
internal reference is used.
2.2 Signal Inputs
The ADC12QS065 has 4 input channels. They are labelled
V
IN
1+
and
VIN1−
,
VIN
2+
and
VIN2−
,
VIN
3+
and
VIN3−
,
VIN
4+ and VIN4− . The input signal, VIN, is defined as
VIN = (VIN+) – (VIN−)
Figure 2 shows the expected input signal range. Note that
the common mode input voltage, VCM, should be in the
range of 0.5V to 2.0V with a typical value of 1.5V.
The peaks of the individual input signals should each never
exceed 2.6V to maintain THD and SINAD performance.
The ADC12QS065 performs best with a differential input
signal with each input centered around a common mode
voltage, VCM. The peak-to-peak voltage swing at each ana-
log input pin should not exceed the value of the reference
voltage or the output data will be clipped.
The two input signals should be exactly 180˚ out of phase
from each other and of the same amplitude. For single
frequency inputs, angular errors result in a reduction of the
effective full scale input. For complex waveforms, however,
angular errors will result in distortion.
20106811
FIGURE 2. Expected Input Signal Range
For single frequency sine waves the full scale error in LSB
can be described as approximately
EFS = 4096 ( 1 - sin (90˚ + dev))
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