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EM620FV8B Schematic ( PDF Datasheet ) - Emerging Memory & Logic Solutions

Teilenummer EM620FV8B
Beschreibung 256K x 8 bit Low Power and Low Voltage Full CMOS Static RAM
Hersteller Emerging Memory & Logic Solutions
Logo Emerging Memory & Logic Solutions Logo 




Gesamt 11 Seiten
EM620FV8B Datasheet, Funktion
Document Title
256K x8 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
0.0
0.1
0.2
0.3
0.4
History
Initial Draft
0.1 Revision
0.2 Revision
0.3 Revision
0.4 Revision
Remove BYTE option information
Remove UB, LB information
Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns),
tOE-55(30ns to 25ns), tWP-55(45ns to 40ns),
tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns),
ICC(2mA to 3mA), ICC1(2mA to 3mA)
VIH level change from 2.0V to 2.2V
EM62ww0wF.DaVta8ShBeet4SU.ceomries
Low Power, 256Kx8 SRAM
Draft Date
June 7, 2007
June 15, 2007
June 21, 2007
July 2, 2007
Remark
Aug. 16, 2007
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1






EM620FV8B Datasheet, Funktion
EM62ww0wF.DaVta8ShBeet4SU.ceomries
Low Power, 256Kx8 SRAM
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL1) = 100pF + 1 TTL
CL1) = 30pF + 1 TTL (only 45ns part)
1. Including scope and Jig capacitance
2. R1=3070 ohm,
3. VTM=2.8V
R2=3150 ohm
CL1)
READ CYCLE (Vcc = 2.7V to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
45ns
Min Max
55ns
Min Max
Read cycle time
tRC 45 - 55 -
Address access time
tAA - 45 - 55
Chip select to output
tCO1, tCO2
- 45 - 55
Output enable to valid output
tOE - 25 - 25
Chip select to low-Z output
tLZ1, tLZ2
10 - 10 -
Output enable to low-Z output
tOLZ
5-5-
Chip disable to high-Z output
tHZ1, tHZ2
0 20 0 20
Output disable to high-Z output
tOHZ
0 15 0 20
Output hold from address change
tOH 10 - 10 -
70ns
Min Max
70 -
- 70
- 70
- 35
10 -
5-
0 25
0 25
10 -
VTM3)
R12)
R22)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE (Vcc = 2.7V to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
45ns
Min Max
55ns
Min Max
Write cycle time
tWC 45 - 55 -
Chip select to end of write
tCW1, tCW2 45 - 45 -
Address setup time
tAS 0 - 0 -
Address valid to end of write
tAW 45 - 45 -
Write pulse width
tWP 35 - 40 -
Write recovery time
tWR 0 - 0 -
Write to ouput high-Z
tWHZ
0 15 0 20
Data to write time overlap
tDW 25
25
Data hold from write time
tDH 0 - 0 -
End write to output low-Z
tOW 5 - 5 -
70ns
Min Max
70 -
60 -
0-
60 -
50 -
0-
0 20
30
0-
5-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6

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