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ADC104S101 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC104S101
Beschreibung 4 Channel- 1 MSPS- 10-Bit A/D Converter
Hersteller National Semiconductor
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Gesamt 19 Seiten
ADC104S101 Datasheet, Funktion
May 2005
www.DataSheet4U.com
ADC104S101
4 Channel, 1 MSPS, 10-Bit A/D Converter
General Description
The ADC104S101 is a low-power, four-channel CMOS 10-bit
analog-to-digital converter with a high-speed serial interface.
Unlike the conventional practice of specifying performance
at a single sample rate only, the ADC104S101 is fully speci-
fied over a sample rate range of 500 kSPS to 1 MSPS. The
converter is based on a successive-approximation register
architecture with an internal track-and-hold circuit. It can be
configured to accept up to four input signals at inputs IN1
through IN4.
The output serial data is straight binary, and is compatible
with several standards, such as SPI, QSPI, MICROW-
IRE, and many common DSP serial interfaces.
The ADC104S101 operates with a single supply, that can
range from +2.7V to +5.25V. Normal power consumption
using a +3V or +5V supply is 3.9 mW and 11.4 mW, respec-
tively. The power-down feature reduces the power consump-
tion to just 0.12 µW using a +3.6V supply, or 0.47 µW using
a +5.5V supply.
The ADC104S101 is packaged in a 10-lead MSOP package.
Operation over the industrial temperature range of −40˚C to
+85˚C is guaranteed.
Features
n Specified over a range of sample rates.
n Four input channels
n Variable power management
n Single power supply with 2.7V - 5.25V range
Key Specifications
n DNL
n INL
n SNR
n Power Consumption
— 3V Supply
— 5V Supply
+0.26/−0.16 LSB (typ)
+0.4/−0.1 LSB (typ)
61.7 dB (typ)
3.9 mW (typ)
11.4 mW (typ)
Applications
n Portable Systems
n Remote Data Acquisition
n Instrumentation and Control Systems
Pin-Compatible Alternatives by Resolution and Speed
All devices are fully pin and function compatible.
Resolution
Specified for Sample Rates of:
50 to 200 kSPS
200 to 500 kSPS
500 kSPS to 1 MSPS
12-bit
ADC124S021
ADC124S051
ADC124S101
10-bit
ADC104S021
ADC104S051
ADC104S101
8-bit
ADC084S021
ADC084S051
ADC084S101
Connection Diagram
20125005
TRI-STATE® is a trademark of National Semiconductor Corporation
QSPIand SPIare trademarks of Motorola, Inc.
© 2005 National Semiconductor Corporation DS201250
www.national.com






ADC104S101 Datasheet, Funktion
Timing Diagrams
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20125008
Timing Test Circuit
ADC104S101 Operational Timing Diagram
20125051
ADC104S101 Serial Timing Diagram
20125050
SCLK and CS Timing Parameters
20125006
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ADC104S101 pdf, datenblatt
Typical Performance Characteristics TA = +25˚C, fSAMPLE = 500 kSPS to 1 MSPS,
fSCLK = 8 MHz to 16 MHz, fIN = 40.3 kHz unless otherwise stated. (Continued)
www.DataSheet4U.com
SFDR vs. Clock Frequency
SINAD vs. Clock Frequency
20125041
SFDR vs. Clock Duty Cycle
20125046
SINAD vs. Clock Duty Cycle
20125042
SFDR vs. Input Frequency
20125047
SINAD vs. Input Frequency
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