PDF GS8150V36AB-333 Data sheet ( Hoja de datos )

Número de pieza	GS8150V36AB-333
Descripción	1M x 18/ 512K x 36 18Mb Register-Register Late Write SRAM
Fabricantes	GSI Technology
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No Preview Available ! Product Preview GS8150V18/3w6wAwB.D-3at5a7Sh/3ee3t34U/3.c0o0m/250 119-Bump BGA Commercial Temp Industrial Temp 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM 250 MHz–357 MHz 1.8 V VDD 1.5 V or 1.8 V HSTL I/O Features • Register-Register Late Write mode, Pipelined Read mode • 1.8 V +150/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • ZQ controlled programmable output drivers • Dual Cycle Deselect • Fully coherent read and write pipelines • Byte write operation (9-bit bytes) • Differential HSTL clock inputs, K and K • Asynchronous output enable • Sleep mode via ZZ • IEEE 1149.1 JTAG-compliant Serial Boundary Scan • JEDEC-standard 119-bump BGA package • Pb-Free 119-bump BGA package available Family Overview GS8150V18/36A are 18,874,368-bit (18Mb) high performance SRAMs. This family of wide, very low voltage HSTL I/O SRAMs is designed to operate at the speeds needed to implement economical high performance cache systems. Functional Description Because GS8150V18/36A are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self- timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. GS8150V18/36A support pipelined reads utilizing a rising- edge-triggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol. GS8150V18/36A are implemented with high performance HSTL technology and are packaged in a 119-bump BGA. Mode Control There are two mode control select pins (M1 and M2), which allow the user to set the correct read protocol for the design. The GS8150V18/36A support single clock Pipeline mode, which directly affects the two mode control select pins. In order for the part to fuction correctly, and as specified, M1 must be tied to VSS and M2 must be tied to VDD or VDDQ. This must be set at power-up and should not be changed during operation. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Pipeline Parameter Synopsis Cycle tKHQV Curr (x18) Curr (x36) -357 -333 -300 -250 Unit 2.8 3.0 3.3 4.0 ns 1.4 1.5 1.6 2.0 ns 600 550 500 450 mA 650 600 550 500 mA Rev: 1.04 4/2005 1/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology 1 page Product Preview GS8150V18/3w6wAwB.D-3at5a7Sh/3ee3t34U/3.c0o0m/250 Write Operations Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic 0 on a rising edge of the K clock (and falling edge of the K clock). Late Write In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT SRAMs. Byte Write Control The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins, including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Byte write control inputs are captured by the same clock edge used to capture SW. Example of x36 Byte Write Truth Table Function SW Ba Bb Bc Bd Read HX X X X Write Byte A LL H H H Write Byte B LH L H H Write Byte C LH H L H Write Byte D LH H H L Write all Bytes LL L L L Write Abort LH H H H FLXDrive-II™ HSTL Output Driver Impedance Control HSTL I/O SigmaRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired SRAM driver impedance. The allowable range of RQ to guarantee impedance matching with specified tolerance is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance occurs automatically because driver impedance is affected by drifts in supply voltage and die temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. The SRAM requires 32K start-up clock cycles, selected or deselected, after VDD reaches its operating range to reach its programmed output driver impedance. Rev: 1.04 4/2005 5/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology 5 Page Device Under Test VDDQ = 1.5 V DQ 25Ω ZQ RQ = 250Ω AC Test Load Diagram 50Ω 5pF 50Ω Product Preview GS8150V18/3w6wAwB.D-3at5a7Sh/3ee3t34U/3.c0o0m/250 VDDQ/2 VDDQ/2 50Ω 50Ω 5pF VDDQ/2 Input and Output Leakage Characteristics Parameter Input Leakage Current (except mode pins) ZQ, MCH, MCL, EP2, EP3 Pin Input Current Symbol IIL IINM Output Leakage Current IOL Test Conditions VIN = 0 to VDDQ VIN = 0 to VDDQ Output Disable, VOUT = 0 to VDDQ Min. –2 uA –50 uA –2 uA Max 2 uA 50 uA 2 uA Notes — — — Operating Currents Parameter Symbol Operating Current x36 x18 IDD IDD HSTL Deselect Current IDD3 -357 0°C –40°C to to 70°C +85°C 650 mA 660 mA 600 mA 610 mA 150 mA 160 mA -333 0°C –40°C to to 70°C +85°C 600 mA 610 mA 550 mA 560 mA 150 mA 160 mA -300 0°C –40°C to to 70°C +85°C 550 mA 560 mA 500 mA 510 mA 150 mA 160 mA -250 0°C –40°C to to 70°C +85°C 500 mA 510 mA 450 mA 460 mA 150 mA 160 mA Test Conditions SS ≤ VIL Max. tKHKH ≥ tKHKH Min. All other inputs VIL ≥ VIN ≥ VIH Device Deselected All inputs VSS + 0.10 V ≥ VIN ≥ VDD – 0.10 V Rev: 1.04 4/2005 11/25 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology 11 Page

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