DS3172 Datasheet PDF - Maxim Integrated
| Part Number | DS3172 | |
| Description | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers | |
| Manufacturers | Maxim Integrated | |
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www.maxim-ic.com
www.DataSheet4U.com
DS3171/DS3172/DS3173/DS3174
Single/Dual/Triple/Quad
DS3/E3 Single-Chip Transceivers
GENERAL DESCRIPTION
The DS3171, DS3172, DS3173, and DS3174
(DS317x) combine a DS3/E3 framer(s) and LIU(s) to
interface to as many as four DS3/E3 physical copper
lines.
APPLICATIONS
Access Concentrators
SONET/SDH ADM
and Muxes
PBXs
Digital Cross Connect
Test Equipment
Routers and Switches
Multiservice Access
Platform (MSAP)
Multiservice Protocol
Platform (MSPP)
PDH Multiplexer/
Demultiplexer
Integrated Access Device
(IAD)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS3171*
DS3171N*
DS3172*
DS3172N*
DS3173*
DS3173N*
DS3174
DS3174N
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
*Future product—contact factory for availability.
FUNCTIONAL DIAGRAM
DS3/E3
PORTS
DS3/
E3
LIU
DS3/E3
FRAMER/
FORMATTER
SYSTEM
BACKPLANE
DS317x
FEATURES
§ Single (DS3171), Dual (DS3172), Triple
(DS3173), or Quad (DS3174) Single-Chip
Transceiver for DS3 and E3
§ All Four Devices are Pin Compatible for Ease of
Port Density Migration in the Same Printed
Circuit Board Platform
§ Each Port Independently Configurable
§ Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3
§ Jitter Attenuator can be Placed Either in the
Receive or Transmit Paths
§ Interfaces to 75W Coaxial Cable at Lengths Up to
380 meters, or 1246 feet (DS3) or 440 meters, or
1443 feet (E3)
§ Uses 1:2 Transformers on Both Tx and Rx
§ On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer(s)
§ Ports Independently Configurable for DS3, E3
§ Built-In HDLC Controllers with 256-Byte FIFOs
for the Insertion/Extraction of DS3 PMDL, G.751
Sn Bit, and G.832 NR/GC Bytes
§ On-Chip BERTs for PRBS and Repetitive Pattern
Generation, Detection, and Analysis
§ Large Performance-Monitoring Counters for
Accumulation Intervals of at Least 1 Second
§ Flexible Overhead Insertion/Extraction Ports for
DS3, E3 Framers
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 102204
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DS3171/DS3172/DS3173/DS3174
www.DataSheet4U.com
10.2.2 Sources of Clock Output Pin Signals ................................................................................................... 54
10.2.3 Line IO Pin Timing Source Selection ................................................................................................... 57
10.2.4 Clock Structures On Signal IO Pins ..................................................................................................... 59
10.2.5 Gapped Clocks..................................................................................................................................... 60
10.3 RESET AND POWER-DOWN ............................................................................................................................ 60
10.4 GLOBAL RESOURCES..................................................................................................................................... 63
10.4.1 Clock Rate Adapter (CLAD) ................................................................................................................. 63
10.4.2 8 kHz Reference Generation ............................................................................................................... 64
10.4.3 One Second Reference Generation..................................................................................................... 66
10.4.4 General-Purpose IO Pins ..................................................................................................................... 66
10.4.5 Performance Monitor Counter Update Details ..................................................................................... 67
10.4.6 Transmit Manual Error Insertion .......................................................................................................... 68
10.5 PER PORT RESOURCES ................................................................................................................................. 69
10.5.1 Loopbacks ............................................................................................................................................ 69
10.5.2 Loss Of Signal Propagation ................................................................................................................. 71
10.5.3 AIS Logic .............................................................................................................................................. 71
10.5.4 Loop Timing Mode ............................................................................................................................... 74
10.5.5 HDLC Overhead Controller .................................................................................................................. 74
10.5.6 Trail Trace ............................................................................................................................................ 74
10.5.7 BERT.................................................................................................................................................... 74
10.5.8 SCT port pins ....................................................................................................................................... 74
10.5.9 Framing Modes .................................................................................................................................... 76
10.5.10 Line Interface Modes............................................................................................................................ 76
10.6 DS3/E3 FRAMER / FORMATTER ..................................................................................................................... 78
10.6.1 General Description ............................................................................................................................. 78
10.6.2 Features ............................................................................................................................................... 78
10.6.3 Transmit Formatter............................................................................................................................... 79
10.6.4 Receive Framer.................................................................................................................................... 79
10.6.5 C-bit DS3 Framer/Formatter ................................................................................................................ 83
10.6.6 M23 DS3 Framer/Formatter ................................................................................................................. 86
10.6.7 G.751 E3 Framer/Formatter................................................................................................................. 88
10.6.8 G.832 E3 Framer/Formatter................................................................................................................. 90
10.7 HDLC OVERHEAD CONTROLLER.................................................................................................................... 95
10.7.1 General Description ............................................................................................................................. 95
10.7.2 Features ............................................................................................................................................... 96
10.7.3 Transmit FIFO ...................................................................................................................................... 96
10.7.4 Transmit HDLC Overhead Processor .................................................................................................. 97
10.7.5 Receive HDLC Overhead Processor ................................................................................................... 97
10.7.6 Receive FIFO ....................................................................................................................................... 98
10.8 TRAIL TRACE CONTROLLER............................................................................................................................ 99
10.8.1 General Description ............................................................................................................................. 99
10.8.2 Features ............................................................................................................................................... 99
10.8.3 Functional Description........................................................................................................................ 100
10.8.4 Transmit Data Storage ....................................................................................................................... 100
10.8.5 Transmit Trace ID Processor ............................................................................................................. 100
10.8.6 Transmit Trail Trace Processing ........................................................................................................ 100
10.8.7 Receive Trace ID Processor .............................................................................................................. 100
10.8.8 Receive Trail Trace Processing ......................................................................................................... 101
10.8.9 Receive Data Storage ........................................................................................................................ 101
10.9 FEAC CONTROLLER ................................................................................................................................... 102
10.9.1 General Description ........................................................................................................................... 102
10.9.2 Features ............................................................................................................................................. 102
10.9.3 Functional Description........................................................................................................................ 102
10.10 LINE ENCODER/DECODER............................................................................................................................ 104
10.10.1 General Description ........................................................................................................................... 104
10.10.2 Features ............................................................................................................................................. 104
10.10.3 B3ZS/HDB3 Encoder ......................................................................................................................... 104
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| Information | Total 30 Pages | |
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