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PDF DS3170 Data sheet ( Hoja de datos )

Número de pieza DS3170
Descripción DS3/E3 Single-Chip Transceiver
Fabricantes Maxim Integrated　
Logotipo Maxim Integrated Logotipo



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PRODUCT BRIEF
www.DataSheet4U.com
DS3170
DS3/E3 Single-Chip Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS3170 combines a DS3/E3 framer and an LIU
(single-chip transceiver) to interface to a DS3/E3
physical copper line.
APPLICATIONS
Access Concentrators
Routers and Switches
SONET/SDH ADM
SONET/SDH Muxes
Multiservice Access
Platforms (MSAPs)
Multiservice Protocol
Platform (MSPPs)
PBXs
PDH Multiplexer/
Demultiplexer
Test Equipment
Digital Cross Connect
Integrated-Access Device
(IAD)
ORDERING INFORMATION
PART
DS3170
DS3170L
DS3170N
DS3170LN
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
100 CSBGA (11mm x
11mm, 1mm pitch)
100 LQFP (14mm x
14mm, 1.4mm pitch)
100 CSBGA (11mm x
11mm, 1mm pitch)
100 LQFP (14mm x
14mm, 1.4mm pitch)
FUNCTIONAL DIAGRAM
DS3/E3 LINE
DS3/
E3
LIU
DS3/E3
FRAMER/
FORMATTER
DS3170
SYSTEM
BACKPLANE
FEATURES
§ Single-Chip Transceiver for DS3 and E3
§ Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3
§ Jitter Attenuator can be Placed Either in the
Receive or Transmit Path
§ Interfaces to 75W Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3), or 440 Meters or
1443 Feet (E3)
§ Uses 1:2 Transformers on Both Tx and Rx
§ On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer
§ Built-In HDLC Controller with 256-Byte FIFO for
the Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes
§ On-Chip BERT for PRBS and Repetitive Pattern
Generation, Detection and Analysis
§ Large Performance-Monitoring Counters for
Accumulation Intervals of At Least 1 Second
§ Flexible Overhead Insertion/Extraction Port for
DS3, E3 Framers
§ Loopbacks Include Line, Diagnostic, Framer,
Payload, and Analog with Capabilities to Insert
AIS in the Directions Away from Loopback
Directions
§ Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz (DS3)
and 34.368MHz (E3) from a Single-Clock
Reference Source
§ CLAD Reference Clock can be 44.736MHz,
34.368MHz, 77.76MHz, 51.84MHz, or 19.44MHz
§ Software Compatible with DS3171–DS3174 SCT
Product Family
§ 8-/16-Bit Parallel and Slave SPI Serial (≤10Mbps)
Microprocessor Interface
§ Low-Power (0.5W) 3.3V Operation (5V Tolerant
I/O)
§ 100-Pin Small 11mm (1mm) CSBGA and 14mm
(1.4mm) LQFP Package Options
§ Industrial Temperature Operation: -40°C to +85°C
§ IEEE1149.1 JTAG Test Port
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS3170 pdf
DS3170 DS3/E3 Single-Chip Transceiver
9.2.5 Gapped Clocks..........................................................................................................w..w...w....D..a..t.a..S.h..e..e..t.4..U...c6o3m
9.3 RESET AND POWER-DOWN ............................................................................................................................ 63
9.4 GLOBAL RESOURCES..................................................................................................................................... 66
9.4.1 Clock Rate Adapter (CLAD) ................................................................................................................. 66
9.4.2 8 kHz Reference Generation ............................................................................................................... 66
9.4.3 One Second Reference Generation..................................................................................................... 67
9.4.4 General-Purpose IO Pins ..................................................................................................................... 68
9.4.5 Performance Monitor Counter Update Details ..................................................................................... 69
9.4.6 Transmit Manual Error Insertion .......................................................................................................... 70
9.5 PORT RESOURCES ........................................................................................................................................ 71
9.5.1 Loopbacks ............................................................................................................................................ 71
9.5.2 Loss Of Signal Propagation ................................................................................................................. 73
9.5.3 AIS Logic .............................................................................................................................................. 73
9.5.4 Loop Timing Mode ............................................................................................................................... 75
9.5.5 HDLC Overhead Controller .................................................................................................................. 75
9.5.6 Trail Trace ............................................................................................................................................ 75
9.5.7 BERT.................................................................................................................................................... 75
9.5.8 System Port Pins.................................................................................................................................. 76
9.5.9 Framing Modes .................................................................................................................................... 77
9.5.10 Line Interface Modes............................................................................................................................ 77
9.6 DS3/E3 FRAMER / FORMATTER ..................................................................................................................... 79
9.6.1 General Description ............................................................................................................................. 79
9.6.2 Features ............................................................................................................................................... 79
9.6.3 Transmit Formatter............................................................................................................................... 80
9.6.4 Receive Framer.................................................................................................................................... 80
9.6.5 C-bit DS3 Framer/Formatter ................................................................................................................ 84
9.6.6 M23 DS3 Framer/Formatter ................................................................................................................. 87
9.6.7 G.751 E3 Framer/Formatter................................................................................................................. 89
9.6.8 G.832 E3 Framer/Formatter................................................................................................................. 91
9.7 HDLC OVERHEAD CONTROLLER.................................................................................................................... 96
9.7.1 General Description ............................................................................................................................. 96
9.7.2 Features ............................................................................................................................................... 97
9.7.3 Transmit FIFO ...................................................................................................................................... 97
9.7.4 Transmit HDLC Overhead Processor .................................................................................................. 98
9.7.5 Receive HDLC Overhead Processor ................................................................................................... 98
9.7.6 Receive FIFO ....................................................................................................................................... 99
9.8 TRAIL TRACE CONTROLLER............................................................................................................................ 99
9.8.1 General Description ............................................................................................................................. 99
9.8.2 Features ............................................................................................................................................. 100
9.8.3 Functional Description........................................................................................................................ 100
9.8.4 Transmit Data Storage ....................................................................................................................... 101
9.8.5 Transmit Trace ID Processor ............................................................................................................. 101
9.8.6 Transmit Trail Trace Processing ........................................................................................................ 101
9.8.7 Receive Trace ID Processor .............................................................................................................. 101
9.8.8 Receive Trail Trace Processing ......................................................................................................... 101
9.8.9 Receive Data Storage ........................................................................................................................ 102
9.9 FEAC CONTROLLER ................................................................................................................................... 102
9.9.1 General Description ........................................................................................................................... 102
9.9.2 Features ............................................................................................................................................. 103
9.9.3 Functional Description........................................................................................................................ 103
9.10 LINE ENCODER/DECODER............................................................................................................................ 104
9.10.1 General Description ........................................................................................................................... 104
9.10.2 Features ............................................................................................................................................. 105
9.10.3 B3ZS/HDB3 Encoder ......................................................................................................................... 105
9.10.4 Transmit Line Interface ...................................................................................................................... 105
9.10.5 Receive Line Interface ....................................................................................................................... 106
9.10.6 B3ZS/HDB3 Decoder ......................................................................................................................... 106
9.11 BERT......................................................................................................................................................... 108
9.11.1 General Description ........................................................................................................................... 108
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DS3170 arduino
DS3170 DS3/E3 Single-Chip Transceiver
Table 11-19. FEAC Receive Side Register Map ............................................................................w..w...w....D..a..t.a..S.h..e..e..t.4..U1.c6o5m
Table 11-20. Transmit Side Trail Trace Register Map............................................................................................. 168
Table 11-21. Trail Trace Receive Side Register Map.............................................................................................. 169
Table 11-22. Transmit DS3 Framer Register Map .................................................................................................. 174
Table 11-23. Receive DS3 Framer Register Map ................................................................................................... 176
Table 11-24. Transmit G.751 E3 Framer Register Map .......................................................................................... 183
Table 11-25. Receive G.751 E3 Framer Register Map ........................................................................................... 186
Table 11-26. Transmit G.832 E3 Framer Register Map .......................................................................................... 191
Table 11-27. Receive G.832 E3 Framer Register Map ........................................................................................... 194
Table 12-1. JTAG Instruction Codes ....................................................................................................................... 205
Table 12-2. JTAG ID Codes .................................................................................................................................... 206
Table 13-1. DS3170 Pin Assignments for 100-Pin LQFP (Sorted by Signal Name)............................................... 208
Table 13-2. DS3170 Pin Assignments for 100-Pin LQFP (Sorted by Pin #) ........................................................... 209
Table 13-3. DS3170 Pin Assignments for 100-Ball CSBGA (Sorted by Signal Name)........................................... 210
Table 13-4. DS3170 Pin Assignments for 100-Ball CSBGA (Sorted by Ball #) ...................................................... 211
Table 15-1. Thermal Information for 100-Pin CSBGA ............................................................................................. 215
Table 15-2. Thermal Information for 100-Pin LQFP ................................................................................................ 215
Table 16-1. Recommended DC Operating Conditions ............................................................................................ 216
Table 16-2. DC Electrical Characteristics ................................................................................................................ 216
Table 16-3. Output Pin Drive ................................................................................................................................... 217
Table 17-1. Framer Interface Timing ....................................................................................................................... 220
Table 17-2. System Port Interface Timing ............................................................................................................... 220
Table 17-3. Misc Timing .......................................................................................................................................... 221
Table 17-4. Overhead Port Timing .......................................................................................................................... 221
Table 17-5. SPI Bus Mode Timing........................................................................................................................... 222
Table 17-6. Micro Interface Timing .......................................................................................................................... 224
Table 17-7. DS3 Waveform Template ..................................................................................................................... 227
Table 17-8. DS3 Waveform Test Parameters and Limits ........................................................................................ 227
Table 17-9. E3 Waveform Test Parameters and Limits........................................................................................... 228
Table 17-10. Receiver Input Characteristics—DS3 Mode....................................................................................... 230
Table 17-11. Receiver Input Characteristics—E3 Mode ......................................................................................... 230
Table 17-12. Transmitter Output Characteristics—DS3 Modes .............................................................................. 231
Table 17-13. Transmitter Output Characteristics—E3 Mode................................................................................... 231
Table 17-14. JTAG Interface Timing........................................................................................................................ 232
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