Datenblatt-pdf.com


ADC12DL065 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer ADC12DL065
Beschreibung Dual 12-Bit/ 65 MSPS/ 3.3V/ 360mW A/D Converter
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 26 Seiten
ADC12DL065 Datasheet, Funktion
May 2005
www.DataSheet4U.com
ADC12DL065
Dual 12-Bit, 65 MSPS, 3.3V, 360mW A/D Converter
General Description
The ADC12DL065 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 12-bit digital words at 65 Megasamples per
second (MSPS). This converter uses a differential, pipeline
architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize power consumption
while providing excellent dynamic performance and a 250
MHz Full Power Bandwidth. Operating on a single +3.3V
power supply, the ADC12DL065 achieves 11.0 effective bits
at nyquist and consumes just 360 mW at 65 MSPS, including
the reference current. The Power Down feature reduces
power consumption to 36 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times VREF with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. The digital outputs from
the two ADC’s are available on a single multiplexed 12-bit
bus or on separate buses. Duty cycle stabilization and output
data format are selectable using a quad state function pin.
The output data can be set for offset binary or two’s comple-
ment.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC12DL065 can be con-
nected to a separate supply voltage in the range of 2.4V to
the analog supply voltage. This device is available in the
64-lead TQFP package and will operate over the industrial
temperature range of −40˚C to +85˚C. An evaluation board is
available to ease the evaluation process.
Features
n Single +3.3V supply operation
n Internal sample-and-hold
n Internal reference
n Outputs 2.4V to 3.6V compatible
n Power down mode
n Duty Cycle Stabilizer
n Multiplexed Output Mode
Key Specifications
n Resolution
n DNL
n SNR (fIN = 10 MHz)
n SFDR (fIN = 10 MHz)
n Data Latency
n Power Consumption
n -- Operating
n -- Power Down Mode
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends
12 Bits
±0.4 LSB (typ)
69 dB (typ)
86 dB (typ)
7 Clock Cycles
360 mW (typ)
36 mW (typ)
Connection Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation DS201001
20100101
www.national.com






ADC12DL065 Datasheet, Funktion
Converter Electrical Characteristics (Continued)
www.DataSheet4U.com
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,
parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical Limits
(Note 10) (Note 10)
Units
(Limits)
FPBW Full Power Bandwidth
0 dBFS Input, Output at −3 dB
250
MHz
SNR
Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
THD
Total Harmonic Distortion
H2 Second Harmonic Distortion
H3 Third Harmonic Distortion
SFDR Spurious Free Dynamic Range
IMD Intermodulation Distortion
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 32.5 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 32.5 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 32.5 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 32.5 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 32.5 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 32.5 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 32.5 MHz, VIN = −0.5 dBFS
fIN = 9.6 MHz and 10.2 MHz,
each = −6.0 dBFS
69
69
68.5
68.5
68.5
68
11.1
11.1
11.0
−82
−83.5
−83
−88
−90
−90
−88
−86
−84
86
86
85
−74
67.5
67
67.5
67
10.9
10.8
-75
-75
-80
-80
-78.5
-77
78.5
77
dBc
dBc (min)
dBc (min)
dBc
dBc (min)
dBc (min)
Bits
Bits (min)
Bits (min)
dBc
dBc (min)
dBc (min)
dBc
dBc (min)
dBc (min)
dBc
dBc (min)
dBc (min)
dBc
dBc (min)
dBc (min)
dBFS
INTER-CHANNEL CHARACTERISTICS
Channel — Channel Offset Match
±0.3
%FS
Channel — Channel Gain Match
±4 %FS
Crosstalk
10 MHz Tested, Channel;
32.5 MHz Other Channel
10 MHz Tested, Channel;
65 MHz Other Channel
90
90
dBc
dBc
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,
parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical Limits
(Note 10) (Note 10)
Units
(Limits)
CLK, PD, OEA, OEB DIGITAL INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
IIN(1)
Logical “1” Input Current
VIN = 3.3V
IIN(0)
Logical “0” Input Current
VIN = 0V
CIN Digital Input Capacitance
DA0–DA11, DB0-DB11 DIGITAL OUTPUT CHARACTERISTICS
2.0 V (min)
1.0 V (max)
10 µA
−10 µA
5 pF
www.national.com
6

6 Page









ADC12DL065 pdf, datenblatt
Typical Performance Characteristics DNL, INL Unless otherwise specified, the following
specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR = +2.5V, PD = 0Vw, VwRwE.FD=at+a1S.h0eVe, tf4CULK.c=om65
MHz, fIN = 0, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ =
TMIN to TMAX: all other limits TJ = 25˚C
DNL
INL
DNL vs. fCLK
20100141
INL vs. fCLK
20100145
DNL vs. Clock Duty Cycle
20100142
INL vs. Clock Duty Cycle
20100146
www.national.com
20100143
12
20100147

12 Page





SeitenGesamt 26 Seiten
PDF Download[ ADC12DL065 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADC12DL065Dual 12-Bit/ 65 MSPS/ 3.3V/ 360mW A/D ConverterNational Semiconductor
National Semiconductor
ADC12DL065Dual 12-Bit / 65 MSPS / 3.3V - 360mW A/D ConverterNational Semiconductor
National Semiconductor
ADC12DL065ADC12DL065 Dual 12-Bit 65 MSPS 3.3V 360mW A/D Converter (Rev. D)Texas Instruments
Texas Instruments
ADC12DL066Dual 12-Bit/ 66Msps/ 450MHz Input Bandwidth A/D Converter w/Internal ReferenceNational Semiconductor
National Semiconductor
ADC12DL066Dual 12-Bit - 66Msps - 450MHz Input Bandwidth A/D Converter w/Internal ReferenceNational Semiconductor
National Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche