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R4F2164 Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R4F2164
Beschreibung 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 30 Seiten
R4F2164 Datasheet, Funktion
REJ09B0429-0100
www.DataSheet4U.com
16
H8S/2164 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2400 Series
H8S/2164 R4F2164
Rev.1.00
Revision Date: Mar. 17, 2008






R4F2164 Datasheet, Funktion
Preface
www.DataSheet4U.com
The H8S/2164 Group products are single-chip microcomputers made up of the high-speed
H8S/2600 CPU employing Renesas Technology original architecture as its core, and the
peripheral functions required to configure a system. The H8S/2600 CPU has an instruction set that
is compatible with the H8/300 and H8/300H CPUs.
Target Users: This manual was written for users who will be using the H8S/2164 Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2164 Group to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a
detailed description of the instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
In order to understand the details of the CPU’s functions
Read the H8S/2600 Series, H8S/2000 Series Software Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 25,
List of Registers.
Examples: Register name:
The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev. 1.00 Mar. 17, 2008 Page vi of xl

6 Page









R4F2164 pdf, datenblatt
7.2.5 DTC Transfer Count Register A (CRA) ............................................................... 156
7.2.6 DTC Transfer Count Register B (CRB)................................................................ 156
7.2.7 DTC Enable Registers (DTCER)..................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m...... 156
7.2.8 DTC Vector Register (DTVECR)......................................................................... 157
7.2.9 Keyboard Comparator Control Register (KBCOMP)........................................... 158
7.2.10 Event Counter Control Register (ECCR).............................................................. 159
7.2.11 Event Counter Status Register (ECS) ................................................................... 160
7.3 DTC Event Counter ........................................................................................................... 161
7.3.1 Event Counter Handling Priority .......................................................................... 162
7.3.2 Usage Notes .......................................................................................................... 163
7.4 Activation Sources............................................................................................................. 163
7.5 Location of Register Information and DTC Vector Table ................................................. 165
7.6 Operation ........................................................................................................................... 167
7.6.1 Normal Mode........................................................................................................ 168
7.6.2 Repeat Mode......................................................................................................... 169
7.6.3 Block Transfer Mode ............................................................................................ 170
7.6.4 Chain Transfer ...................................................................................................... 171
7.6.5 Interrupt Sources................................................................................................... 172
7.6.6 Operation Timing.................................................................................................. 172
7.6.7 Number of DTC Execution States ........................................................................ 173
7.7 Procedures for Using DTC................................................................................................. 175
7.7.1 Activation by Interrupt.......................................................................................... 175
7.7.2 Activation by Software ......................................................................................... 175
7.8 Examples of Use of the DTC ............................................................................................. 176
7.8.1 Normal Mode........................................................................................................ 176
7.8.2 Software Activation .............................................................................................. 177
7.9 Usage Notes ....................................................................................................................... 178
7.9.1 Module Stop Mode Setting ................................................................................... 178
7.9.2 On-Chip RAM ...................................................................................................... 178
7.9.3 DTCE Bit Setting.................................................................................................. 178
7.9.4 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter .................. 178
Section 8 I/O Ports............................................................................................. 179
8.1 Port 1.................................................................................................................................. 184
8.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 184
8.1.2 Port 1 Data Register (P1DR) ................................................................................ 185
8.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)................................................... 185
8.1.4 Pin Functions ........................................................................................................ 186
8.1.5 Port 1 Input Pull-Up MOS .................................................................................... 186
8.2 Port 2.................................................................................................................................. 187
8.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 187
8.2.2 Port 2 Data Register (P2DR) ................................................................................ 188
8.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)................................................... 188
8.2.4 Pin Functions ........................................................................................................ 189
Rev. 1.00 Mar. 17, 2008 Page xii of xl

12 Page





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