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PDF R4F2117 Data sheet ( Hoja de datos )
| Número de pieza | R4F2117 | |
| Descripción | Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series | |
| Fabricantes | Renesas Technology | |
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REJ09B0350-0200
www.DataSheet4U.com
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2117Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2100 Series
H8S/2117
R4F2117
All information contained in this material, including products and product
specifications at the time of publication of this material, is subject to change by
Renesas Technology Corp. without notice. Please review the latest information
published by Renesas Technology Corp. through various means, including the
Renesas Technology Corp. website (http://www.renesas.com).
Rev.2.00
Revision Date: Feb. 20, 2008
1 page  
How to Use This Manual
www.DataSheet4U.com
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this
LSI to the target users, i.e. those who will be using this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical circuits, logic
circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of
the CPU, system control functions, and peripheral functions, electrical characteristics of the
device, and usage notes.
When designing an application system that includes this LSI, take all points to note into
account. Points to note are given in their contexts and at the final part of each section, and
in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions.
It does not cover all revised items. For details on the revised points, see the actual locations
in the manual.
The following documents have been prepared for the H8S/2117 Group. Before using any of
the documents, please visit our web site to verify that you have the most up-to-date available
version of the document.
Document Type
Data Sheet
Hardware Manual
Software Manual
Application Note
Renesas Technical
Update
Contents
Document Title
Document No.
Overview of hardware and electrical
characteristics
Hardware specifications (pin
assignments, memory maps,
peripheral specifications, electrical
characteristics, and timing charts)
and descriptions of operation
H8S/2117 Group
Hardware Manual
This manual
Detailed descriptions of the CPU
and instruction set
H8S/2600 Series
REJ09B0139
H8S/2000 Series Software
Manual
Examples of applications and
sample programs
The latest versions are available from our
web site.
Preliminary report on the
specifications of a product,
document, etc.
Rev. 2.00 Feb. 20, 2008 Page v of xxiv
5 Page 
5.3.2 Address Break Control Register (ABRKCR) ......................................................... 91
5.3.3 Break Address Registers A to C (BARA to BARC) ...w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m.......... 92
5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) ................... 93
5.3.5 IRQ Enable Registers (IER16, IER) ....................................................................... 96
5.3.6 IRQ Status Registers (ISR16, ISR) ......................................................................... 97
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA KMIMR)
Wake-Up Event Interrupt Mask Registers (WUEMR) ........................................... 99
5.3.8 IRQ Sense Port Select Register 16 (ISSR16)
IRQ Sense Port Select Register (ISSR)................................................................. 103
5.3.9 Wake-Up Sense Control Register (WUESCR) Wake-Up Input
Interrupt Status Register (WUESR) Wake-Up Enable Register (WER)............... 104
5.4 Interrupt Sources................................................................................................................ 105
5.4.1 External Interrupt Sources .................................................................................... 105
5.4.2 Internal Interrupt Sources ..................................................................................... 108
5.5 Interrupt Exception Handling Vector Tables ..................................................................... 108
5.6 Interrupt Control Modes and Interrupt Operation .............................................................. 117
5.6.1 Interrupt Control Mode 0 ...................................................................................... 119
5.6.2 Interrupt Control Mode 1 ...................................................................................... 121
5.6.3 Interrupt Exception Handling Sequence ............................................................... 124
5.6.4 Interrupt Response Times ..................................................................................... 125
5.7 Address Breaks .................................................................................................................. 126
5.7.1 Features................................................................................................................. 126
5.7.2 Block Diagram...................................................................................................... 126
5.7.3 Operation .............................................................................................................. 127
5.7.4 Usage Notes .......................................................................................................... 127
5.8 Usage Notes ....................................................................................................................... 129
5.8.1 Conflict between Interrupt Generation and Disabling .......................................... 129
5.8.2 Instructions for Disabling Interrupts ..................................................................... 130
5.8.3 Interrupts during Execution of EEPMOV Instruction........................................... 130
5.8.4 Vector Address Switching .................................................................................... 130
5.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode.................... 131
5.8.6 Noise Canceller Switching.................................................................................... 131
5.8.7 IRQ Status Register (ISR)..................................................................................... 131
Section 6 Bus Controller (BSC).........................................................................133
6.1 Register Descriptions ......................................................................................................... 133
6.1.1 Bus Control Register (BCR) ................................................................................. 133
6.1.2 Wait State Control Register (WSCR) ................................................................... 134
Rev. 2.00 Feb. 20, 2008 Page xi of xxiv
11 Page | ||
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