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R4F2112 Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R4F2112
Beschreibung 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 30 Seiten
R4F2112 Datasheet, Funktion
REJ09B0451-0100
www.DataSheet4U.com
16
H8S/2112 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2100 Series
H8S/2112
R4F2112
All information contained in this material, including products and product
specifications at the time of publication of this material, is subject to change by
Renesas Technology Corp. without notice. Please review the latest information
published by Renesas Technology Corp. through various means, including the
Renesas Technology Corp. website (http://www.renesas.com).
Rev.1.00
Revision Date: Mar. 18, 2008






R4F2112 Datasheet, Funktion
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, awndwwsy.DmabtoalSihceneatm4Ue.scoinmthis
manual are explained below.
(1) Overall notation
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(2) Register notation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
(3) Number notation
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary:
B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal:
1234
(4) Notation for active-low
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
(4) (2)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(3)
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
Rev. 1.00 Mar. 18, 2008 Page vi of xxiv

6 Page









R4F2112 pdf, datenblatt
6.8.4
6.8.5
6.8.6
6.8.7
Vector Address Switching .................................................................................... 144
External Interrupt Pin in Software Standby Mode and wWwawtc.hDaMtaoSdhee..e..t.4..U....c..o..m...... 145
Noise Canceller Switching.................................................................................... 145
IRQ Status Register (ISR)..................................................................................... 145
Section 7 Bus Controller (BSC) ........................................................................147
7.1 Register Descriptions ......................................................................................................... 147
7.1.1 Bus Control Register (BCR) ................................................................................. 147
7.1.2 Wait State Control Register (WSCR) ................................................................... 148
Section 8 I/O Ports.............................................................................................149
8.1 Register Descriptions ......................................................................................................... 156
8.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to H).............. 157
8.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9).......................................................... 158
8.1.3 Input Data Register (PnPIN) (n = 1 to 9 and A to J)............................................. 158
8.1.4 Pull-Up MOS Control Register (PnPCR) (n = 1 to 3, 6, 9, B to D, F, and H) ...... 159
8.1.5 Output Data Register (PnODR) (n = A to D and F to H)...................................... 160
8.1.6 Noise Canceller Enable Register (PnNCE) (n = 4, 6, C, and G)........................... 161
8.1.7 Noise Canceller Decision Control Register (PnNCMC) (n = 4, 6, C, and G)....... 161
8.1.8 Noise Cancel Cycle Setting Register (PnNCCS) (n = 4, 6, C, and G) .................. 162
8.1.9 Port Nch-OD Control Register (PnNOCR) (n = C, D, F, G, and H)..................... 163
8.1.10 MOS State of Output Buffer ................................................................................. 164
8.2 Pin Functions ..................................................................................................................... 165
8.2.1 Port 1..................................................................................................................... 165
8.2.2 Port 2..................................................................................................................... 165
8.2.3 Port 3..................................................................................................................... 166
8.2.4 Port 4..................................................................................................................... 167
8.2.5 Port 5..................................................................................................................... 170
8.2.6 Port 6..................................................................................................................... 171
8.2.7 Port 7..................................................................................................................... 172
8.2.8 Port 8..................................................................................................................... 172
8.2.9 Port 9..................................................................................................................... 175
8.2.10 Port A.................................................................................................................... 176
8.2.11 Port B.................................................................................................................... 177
8.2.12 Port C.................................................................................................................... 180
8.2.13 Port D.................................................................................................................... 184
8.2.14 Port E .................................................................................................................... 185
8.2.15 Port F .................................................................................................................... 186
8.2.16 Port G.................................................................................................................... 188
8.2.17 Port H.................................................................................................................... 192
Rev. 1.00 Mar. 18, 2008 Page xii of xxiv

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