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PDF PACDN009 Data sheet ( Hoja de datos )
| Número de pieza | PACDN009 | |
| Descripción | 5 Channel ESD Protection Array | |
| Fabricantes | California Micro Devices | |
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5 Channel ESD Protection Array
PACDN009www.DataSheet4U.com
Features
• Five channels of ESD protection
• ±8 kV contact, ±15 kV air ESD protection per
channel (IEC 61000-4-2 standard)
• ±15 kV of ESD protection per channel (HBM)
• Low loading capacitance (3pF typical)
• Low leakage current is ideal for battery-powered
devices
• Available in miniature 8-lead MSOP package
• Lead-free version available
Applications
• Consumer electronic products
• Cellular phones
• PDAs
• Notebook computers
• Desktop PCs
• Digital cameras and camcorders
• VGA (video) port protection for desktop
and portable PCs
Product Description
The PACDN009 is a diode array designed to provide 5
channels of ESD protection for electronic components
or sub-systems. Each channel consists of a pair of
diodes which steers an ESD current pulse to either the
positive (VP) or negative (VN) supply. The PACDN009
protects against ESD pulses up to ±15kV Human Body
Model (100 pF capacitor discharging through a 1.5KΩ
resistor), and ±8kV contact discharge, per International
Standard IEC 61000-4-2.
This device is particularly well-suited for portable elec-
tronics (e.g., cellular phones, PDAs, notebook comput-
ers) because of its small package footprint, high ESD
protection level, and low loading capacitance. It is also
suitable for protecting video output lines and I/O ports
in computers and peripherals and is ideal for a wide
range of consumer electronics products.
The PACDN009 is supplied in an 8-lead MSOP pack-
age and is available with optional lead-free finishing.
Typical Application Circuit
Electrical Schematic
I/O Port
Buffers
3 PACDN009 7
14 56 8
0.22µF*
Expansion
Connector
Handheld/PDA ESD Protection
* Capacitor should be placed
as close as possible to Pin7
8765
VP
VN
N.C.
1234
© 2004 California Micro Devices Corp. All rights reserved.
09/21/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com
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1 page  
PACDN009www.DataSheet4U.com
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 1, which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductances back to
the power supply are represented by L1 and L2. The
voltage VCL on the line being protected is:
VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt
+ L2 x d(IESD ) / dt
where IESD is the ESD current pulse, and VSUPPLY is
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
A∆ImESpDs/∆int,1onrs3. 0H/(e1rxe1d0(-I9E)S. DS)o/djtucsat n10bneHaopfprsoexriimesatienddubcy-
tance (L1 and L2 combined) will lead to a 300V incre-
ment in VCL!
Similarly for negative ESD pulses, parasitic series
inductance from the VN pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
Another consideration is the output impedance of the
power supply for fast transient currents. Most power
supplies exhibit a much higher output impedance to
fast transient current spikes. In the VCL equation
above, the VSUPPLY term, in reality, is given by (VDC +
IESD x ROUT), where VDC and ROUT are the nominal
supply DC output voltage and effective output imped-
ance of the power supply respectively. For example,
with ROUT equal to 1 ohm, we would see a 10V incre-
ment in VCL for a peak IESD of 10A.
If the inductances and resistance described above are
close to zero, the rail-clamp ESD protection diodes will
do a good job of protection. However, since this is not
possible in practical situations, a bypass capacitor
must be used to absorb the very high frequency ESD
energy. So for any brand of rail-clamp ESD protection
diodes, a bypass capacitor should be connected
between the VP pin of the diodes and the ground plane
(VN pin of the diodes) as shown in the Application Cir-
cuit diagram below. A value of 0.22µF is adequate for
IEC-61000-4-2 level 4 contact discharge protection
(±8kV). Ceramic chip capacitors mounted with short
printed circuit board traces are good choices for this
application. Electrolytic capacitors should be avoided
as they have poor high frequency characteristics. For
extra protection, connect a zener diode in parallel with
the bypass capacitor to mitigate the effects of the para-
sitic series inductance inherent in the capacitor. The
breakdown voltage of the zener diode should be
slightly higher than the maximum supply voltage.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the VP pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also California Micro Devices Application Notes
AP209, “Design Considerations for ESD Protection”
and AP219, "ESD Protection for USB 2.0 Systems"”
L2
POSITIVE SUPPLY RAIL
VP
PATH OF ESD CURRENT PULSE IESD
D1
ONE
D2
CHANNEL
OF
PAC DN009
VN
L1
CHANNEL
INPUT
20A
0A
LINE BEING
PROTECTED
VCL
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
GROUND RAIL
CHASSIS GROUND
Figure 1. Application of Positive ESD Pulse between Input Channel and Ground
© 2004 California Micro Devices Corp. All rights reserved.
09/21/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ● Tel: 408.263.3214 ● Fax: 408.263.7846 ● www.calmicro.com
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet PACDN009.PDF ] | |
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