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R5F7142 Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R5F7142
Beschreibung 32-Bit RISC Microcomputer SuperH RISC engine Family
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 70 Seiten
R5F7142 Datasheet, Funktion
REJ09B0230-0300
www.DataSheet4U.com
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and additions.
Details should always be checked by referring to the relevant text.
32
SH7147 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family
SH7147
SH7142
R5F7147
R5F7142
Rev.3.00
Revision Date: Oct. 06, 2008






R5F7142 Datasheet, Funktion
SH7147 Group Manuals:
Document Title
SH7147 Group Hardware Manual
SH-1/SH-2/SH-DSP Software Manual
www.DaDtoacShuemeet4nUt.cNoom.
This manual
REJ09B0171
User's Manuals for Development Tools:
Document Title
SuperHTM RISC engine C/C++ Compiler, Assembler,
Optimizing Linkage Editor Compiler Package V.9.00 User's Manual
SuperHTM RISC engine High-performance Embedded Workshop 3
User's Manual
SuperH RISC engine High-Performance Embedded Workshop 3 Tutorial
Document No.
REJ10B0152
REJ10B0025
REJ10B0023
Application Note:
Document Title
SuperH RISC engine C/C++ Compiler Package Application Note
Document No.
REJ05B0463
All trademarks and registered trademarks are the property of their respective owners.
Rev. 3.00 Oct. 06, 2008 Page vi of xxiv
REJ09B0230-0300

6 Page









R5F7142 pdf, datenblatt
9.4 Register Descriptions........................................................................................................ 207
9.4.1
9.4.2
Common Control Register (CMNCR) ......................w...w..w.....D..a..t.a...S.h..e..e..t.4..U....c..o..m...... 207
CSn Space Bus Control Register (CSnBCR) (n = 0 and 1) .............................. 209
9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 and 1)............................ 212
9.4.4 Bus Function Extending Register (BSCEHR) .................................................. 214
9.5 Operation .......................................................................................................................... 215
9.5.1 Endian/Access Size and Data Alignment.......................................................... 215
9.5.2 Normal Space Interface..................................................................................... 216
9.5.3 Access Wait Control ......................................................................................... 219
9.5.4 CSn Assert Period Extension ............................................................................ 221
9.5.5 Wait between Access Cycles ............................................................................ 222
9.5.6 Bus Arbitration ................................................................................................. 224
9.5.7 Others................................................................................................................ 230
9.5.8 Access to On-Chip FLASH and On-Chip RAM by CPU ................................. 231
9.5.9 Access to On-Chip Peripheral I/O Registers by CPU ....................................... 231
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) and Multi-Function
Timer Pulse Unit 2S (MTU2S) .......................................................235
10.1 Features............................................................................................................................. 235
10.2 Input/Output Pins.............................................................................................................. 246
10.3 Register Descriptions........................................................................................................ 248
10.3.1 Timer Control Register (TCR).......................................................................... 255
10.3.2 Timer Mode Register (TMDR) ......................................................................... 259
10.3.3 Timer I/O Control Register (TIOR) .................................................................. 262
10.3.4 Timer Compare Match Clear Register (TCNTCMPCLR) ................................ 281
10.3.5 Timer Interrupt Enable Register (TIER) ........................................................... 282
10.3.6 Timer Status Register (TSR)............................................................................. 287
10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)............................... 294
10.3.8 Timer Input Capture Control Register (TICCR) ............................................... 295
10.3.9 Timer Synchronous Clear Register (TSYCR)................................................... 297
10.3.10 Timer A/D Converter Start Request Control Register (TADCR) ..................... 299
10.3.11 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4).................................................................. 302
10.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4) ............................................................ 302
10.3.13 Timer Counter (TCNT)..................................................................................... 303
10.3.14 Timer General Register (TGR) ......................................................................... 303
10.3.15 Timer Start Register (TSTR) ............................................................................ 304
10.3.16 Timer Synchronous Register (TSYR)............................................................... 306
10.3.17 Timer Counter Synchronous Start Register (TCSYSTR) ................................. 308
Rev. 3.00 Oct. 06, 2008 Page xii of xxiv
REJ09B0230-0300

12 Page





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