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R5F7136 Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R5F7136
Beschreibung 32-Bit RISC Microcomputer SuperH RISC engine Family
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 70 Seiten
R5F7136 Datasheet, Funktion
REJ09B0402-0200
The revision list can be viewed directly bywww.DataSheet4U.com
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
SH7137 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family
SH7136 R5F7136
SH7137 R5F7137
Rev.2.00
Revision Date: Sep. 10, 2008






R5F7136 Datasheet, Funktion
Preface
www.DataSheet4U.com
The SH7136 and SH7137 Group RISC (Reduced Instruction Set Computer) microcomputers
include a Renesas Technology-original RISC CPU as its core, and the peripheral functions
required to configure a system.
Target Users: This manual was written for users who will be using the SH7136 and SH7137
Group in the design of application systems. Target users are expected to understand
the fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the SH7136 and SH7137 Group to the target users.
Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
In order to understand the details of the CPU's functions
Read the SH-1/SH-2/SH-DSP Software Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 25,
List of Registers.
Examples: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Rev. 2.00 Sep. 10, 2008 Page vi of xxvi

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R5F7136 pdf, datenblatt
Section 7 User Break Controller (UBC)...........................w..w..w....D..a..t.a..S.h..e..e..t4..U...c..o..m.... 121
7.1 Features.............................................................................................................................. 121
7.2 Input/Output Pins............................................................................................................... 123
7.3 Register Descriptions......................................................................................................... 124
7.3.1 Break Address Register A (BARA)...................................................................... 125
7.3.2 Break Address Mask Register A (BAMRA)......................................................... 125
7.3.3 Break Bus Cycle Register A (BBRA)................................................................... 126
7.3.4 Break Data Register A (BDRA) ........................................................................... 128
7.3.5 Break Data Mask Register A (BDMRA) .............................................................. 129
7.3.6 Break Address Register B (BARB) ...................................................................... 130
7.3.7 Break Address Mask Register B (BAMRB) ......................................................... 131
7.3.8 Break Data Register B (BDRB)............................................................................ 132
7.3.9 Break Data Mask Register B (BDMRB)............................................................... 133
7.3.10 Break Bus Cycle Register B (BBRB) ................................................................... 134
7.3.11 Break Control Register (BRCR) ........................................................................... 136
7.3.12 Execution Times Break Register (BETR)............................................................. 141
7.3.13 Branch Source Register (BRSR)........................................................................... 142
7.3.14 Branch Destination Register (BRDR)................................................................... 143
7.4 Operation ........................................................................................................................... 144
7.4.1 Flow of the User Break Operation ........................................................................ 144
7.4.2 User Break on Instruction Fetch Cycle ................................................................. 145
7.4.3 Break on Data Access Cycle................................................................................. 146
7.4.4 Sequential Break................................................................................................... 147
7.4.5 Value of Saved Program Counter ......................................................................... 147
7.4.6 PC Trace ............................................................................................................... 148
7.4.7 Usage Examples.................................................................................................... 149
7.5 Usage Notes ....................................................................................................................... 154
Section 8 Data Transfer Controller (DTC)........................................................ 157
8.1 Features.............................................................................................................................. 157
8.2 Register Descriptions......................................................................................................... 159
8.2.1 DTC Mode Register A (MRA) ............................................................................. 160
8.2.2 DTC Mode Register B (MRB).............................................................................. 161
8.2.3 DTC Source Address Register (SAR)................................................................... 163
8.2.4 DTC Destination Address Register (DAR)........................................................... 163
8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 164
8.2.6 DTC Transfer Count Register B (CRB)................................................................ 165
8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE) ....................................... 166
8.2.8 DTC Control Register (DTCCR) .......................................................................... 167
Rev. 2.00 Sep. 10, 2008 Page xii of xxvi

12 Page





SeitenGesamt 70 Seiten
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