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PDF GS8160V18CT Data sheet ( Hoja de datos )
| Número de pieza | GS8160V18CT | |
| Descripción | 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs | |
| Fabricantes | GSI Technology | |
| Logotipo |  |
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Preliminary
GS8160Vw1w8w/3.D6aCtaTSh-e3e3t43U/3.c0om0/250
100-Pin TQFP
Commercial Temp
Industrial Temp
1M x 18 and 512K x 36
18Mb Sync Burst SRAMs
333 MHz–250 MHz
1.8 V VDD
1.8 V I/O
Features
• FT pin for user-configurable flow through or pipeline
operation
• Single Cycle Deselect (SCD) operation
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS8160V18/36CT is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8160V18/36CT operates on a 1.8 V power supply. All
input are 1.8 V compatible. Separate output power (VDDQ)
pins are used to decouple output noise from the internal circuits
and are 1.8 V compatible.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-333 -300 -250 Unit
tKQ
tCycle
2.5 2.5 2.5 ns
3.0 3.3 4.0 ns
Curr (x18)
Curr (x32/x36)
375 335 280 mA
435 390 330 mA
tKQ
tCycle
4.5 5.0 5.5 ns
4.5 5.0 5.5 ns
Curr (x18)
Curr (x32/x36)
280 230 210 mA
335 270 240 mA
Rev: 1.00 9/2004
1/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
1 page  
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
GS8160V18/36C Block Diagram
Preliminary
GS8160Vw1w8w/3.D6aCtaTSh-e3e3t43U/3.c0om0/250
Register
DQ
A0
A1
D0 Q0
D1 Q1
Counter
Load
A0
A1
Register
DQ
A
Memory
Array
QD
Register
DQ
Register
DQ
36
4
36
Register
DQ
Register
DQ
E1
E2
E3
FT
G
ZZ Power Down
Control
Note: Only x36 version shown for simplicity.
Register
DQ
Register
DQ
1
DQx1–DQx9
Rev: 1.00 9/2004
5/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
5 Page 
Preliminary
GS8160Vw1w8w/3.D6aCtaTSh-e3e3t43U/3.c0o0m/250
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
VDDQ
VI/O
VIN
IIN
IOUT
PD
TSTG
TBIAS
Voltage on VDD Pins
Voltage in VDDQ Pins
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
Temperature Under Bias
–0.5 to 3.6
–0.5 to 3.6
–0.5 to VDDQ +0.5 (≤ 3.6 V max.)
–0.5 to VDD +0.5 (≤ 3.6 V max.)
+/–20
+/–20
1.5
–55 to 125
–55 to 125
V
V
V
V
mA
mA
W
oC
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol Min. Typ. Max. Unit Notes
1.8 V Supply Voltage
VDD1
1.6
1.8
2.0
V
1.8 V VDDQ I/O Supply Voltage
VDDQ1
1.6
1.8
2.0
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.00 9/2004
11/21
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet GS8160V18CT.PDF ] | |
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