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R5M7083 Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R5M7083
Beschreibung 32-Bit RISC Microcomputer SuperH RISC engine Family
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 30 Seiten
R5M7083 Datasheet, Funktion
REJ09B0181-0300
The revision list can be viewed directly bywww.DataSheet4U.com
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
SH7080 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family
SH7083
SH7084
SH7085
SH7086
R5F7083
R5M7083
R5S7083
R5F7084
R5M7084
R5S7084
R5F7085
R5M7085
R5S7085
R5F7086
Rev.3.00
Revision Date: May 17, 2007






R5M7083 Datasheet, Funktion
Preface
www.DataSheet4U.com
The SH7083, SH7084, SH7085, and SH7086 Group RISC (Reduced Instruction Set Computer)
microcomputers include a Renesas Technology-original RISC CPU as its core, and the peripheral
functions required to configure a system.
Target Users: This manual was written for users who will be using the SH7083, SH7084, SH7085,
and SH7086 Group in the design of application systems. Target users are expected
to understand the fundamentals of electrical circuits, logical circuits, and
microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the SH7083, SH7084, SH7085, and SH7086 Group to the target
users.
Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
In order to understand the details of the CPU's functions
Read the SH-1/SH-2/SH-DSP Software Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 27,
List of Registers.
Examples: Register name: The following notation is used for cases when the same or a
similar function, e.g. serial communication interface, is
implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx
Rev. 3.00 May 17, 2007 Page vi of lviii

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R5M7083 pdf, datenblatt
Section 7 User Break Controller (UBC)............................................................ 135
7.1 Features......................................................................................w..w...w.....D..a..t.a..S..h..e..e..t.4..U....c..o..m...... 135
7.2 Input/Output Pins............................................................................................................... 137
7.3 Register Descriptions......................................................................................................... 138
7.3.1 Break Address Register A (BARA)...................................................................... 139
7.3.2 Break Address Mask Register A (BAMRA)......................................................... 139
7.3.3 Break Bus Cycle Register A (BBRA)................................................................... 140
7.3.4 Break Data Register A (BDRA) (Only in F-ZTAT Version)................................ 142
7.3.5 Break Data Mask Register A (BDMRA) (Only in F-ZTAT Version) .................. 143
7.3.6 Break Address Register B (BARB) ...................................................................... 144
7.3.7 Break Address Mask Register B (BAMRB) ......................................................... 145
7.3.8 Break Data Register B (BDRB) (Only in F-ZTAT Version) ................................ 146
7.3.9 Break Data Mask Register B (BDMRB) (Only in F-ZTAT Version)................... 147
7.3.10 Break Bus Cycle Register B (BBRB) ................................................................... 148
7.3.11 Break Control Register (BRCR) ........................................................................... 150
7.3.12 Execution Times Break Register (BETR) (Only in F-ZTAT Version)................. 155
7.3.13 Branch Source Register (BRSR) (Only in F-ZTAT Version)............................... 156
7.3.14 Branch Destination Register (BRDR) (Only in F-ZTAT Version)....................... 157
7.4 Operation ........................................................................................................................... 158
7.4.1 Flow of the User Break Operation ........................................................................ 158
7.4.2 User Break on Instruction Fetch Cycle ................................................................. 159
7.4.3 User Break on Data Access Cycle ........................................................................ 160
7.4.4 Sequential Break................................................................................................... 161
7.4.5 Value of Saved Program Counter ......................................................................... 161
7.4.6 PC Trace ............................................................................................................... 162
7.4.7 Usage Examples.................................................................................................... 163
7.5 Usage Notes ....................................................................................................................... 168
Section 8 Data Transfer Controller (DTC)........................................................ 171
8.1 Features.............................................................................................................................. 171
8.2 Register Descriptions......................................................................................................... 173
8.2.1 DTC Mode Register A (MRA) ............................................................................. 174
8.2.2 DTC Mode Register B (MRB).............................................................................. 175
8.2.3 DTC Source Address Register (SAR)................................................................... 177
8.2.4 DTC Destination Address Register (DAR)........................................................... 177
8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 178
8.2.6 DTC Transfer Count Register B (CRB)................................................................ 179
8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE) ....................................... 180
8.2.8 DTC Control Register (DTCCR) .......................................................................... 181
8.2.9 DTC Vector Base Register (DTCVBR)................................................................ 183
Rev. 3.00 May 17, 2007 Page xii of lviii

12 Page





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