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Teilenummer | R5S61651C |
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Beschreibung | Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series | |
Hersteller | Renesas Technology | |
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Gesamt 70 Seiten REJ09B0248-0200
www.DataSheet4U.com
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
H8SX/1651Group
Hardware Manual
Renesas 32-Bit CISC Microcomputer
H8SX Family / H8SX/1600 Series
H8SX/1651C R5S61651C
All information contained in this material, including products and product
specifications at the time of publication of this material, is subject to change by
Renesas Technology Corp. without notice. Please review the latest information
published by Renesas Technology Corp. through various means, including the
Renesas Technology Corp. website (http://www.renesas.com).
Rev.2.00
Revision Date: Jun. 28, 2007
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, awnwd wsy.DmabtoalSihceneatm4Ue.scoinmthis
manual are explained below.
(1) Overall notation
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(2) Register notation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
(3) Number notation
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary:
B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal:
1234
(4) Notation for active-low
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
(4) (2)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(3)
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
Rev.2.00 Jun. 28, 2007 Page vi of xxiv
6 Page 5.8.6 Interrupt Source Flag of Peripheral Module ..................................................... 122
www.DataSheet4U.com
Section 6 Bus Controller (BSC) ........................................................................ 123
6.1 Features............................................................................................................................. 123
6.2 Register Descriptions........................................................................................................ 126
6.2.1 Bus Width Control Register (ABWCR)............................................................ 127
6.2.2 Access State Control Register (ASTCR) .......................................................... 128
6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 129
6.2.4 Read Strobe Timing Control Register (RDNCR) ............................................. 134
6.2.5 CS Assertion Period Control Registers (CSACR) ............................................ 135
6.2.6 Idle Control Register (IDLCR) ......................................................................... 138
6.2.7 Bus Control Register 1 (BCR1) ........................................................................ 140
6.2.8 Bus Control Register 2 (BCR2) ........................................................................ 142
6.2.9 Endian Control Register (ENDIANCR) ........................................................... 143
6.2.10 SRAM Mode Control Register (SRAMCR) ..................................................... 144
6.2.11 Burst ROM Interface Control Register (BROMCR) ........................................ 145
6.2.12 Address/Data Multiplexed I/O Control Register (MPXCR) ............................. 147
6.3 Bus Configuration............................................................................................................. 148
6.4 Multi-Clock Function and Number of Access Cycles ...................................................... 149
6.5 External Bus ..................................................................................................................... 153
6.5.1 Input/Output Pins.............................................................................................. 153
6.5.2 Area Division.................................................................................................... 156
6.5.3 Chip Select Signals ........................................................................................... 157
6.5.4 External Bus Interface ...................................................................................... 158
6.5.5 Area and External Bus Interface ....................................................................... 162
6.5.6 Endian and Data Alignment.............................................................................. 167
6.6 Basic Bus Interface ........................................................................................................... 170
6.6.1 Data Bus ........................................................................................................... 170
6.6.2 I/O Pins Used for Basic Bus Interface .............................................................. 170
6.6.3 Basic Timing..................................................................................................... 171
6.6.4 Wait Control ..................................................................................................... 178
6.6.5 Read Strobe (RD) Timing................................................................................. 180
6.6.6 Extension of Chip Select (CS) Assertion Period............................................... 182
6.6.7 DACK Signal Output Timing ........................................................................... 184
6.7 Byte Control SRAM Interface .......................................................................................... 185
6.7.1 Byte Control SRAM Space Setting................................................................... 185
6.7.2 Data Bus ........................................................................................................... 185
6.7.3 I/O Pins Used for Byte Control SRAM Interface ............................................. 186
6.7.4 Basic Timing..................................................................................................... 187
6.7.5 Wait Control ..................................................................................................... 189
Rev.2.00 Jun. 28, 2007 Page xii of xxiv
12 Page | ||
Seiten | Gesamt 70 Seiten | |
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Teilenummer | Beschreibung | Hersteller |
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