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Número de pieza | DG221B | |
Descripción | Quad SPST CMOS Analog Switch | |
Fabricantes | Vishay Siliconix | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de DG221B (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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DG221B
Viswwhwa.DyatSaSihleiceto4Un.cioxm
Quad SPST CMOS Analog Switch with Latches
FEATURES
BENEFITS
APPLICATIONS
D Accepts 150-ns Write Pulse Width
D 5-V On-Chip Regulator
D Latches Are Transparent with WR Low
D Low On-Resistance: 60 W
D Compatible with Most mP Buses
D Allows Wide Power Supply Tolerance
Without Affecting TTL Compatibility
D Reduced Power Consumption
D Allows Flexibility of Design
D mP Based Systems
D Automatic Test Equipment
D Communication Systems
D Data Acquisition Systems
D Medical Instrumentation
D Factory Automation
DESCRIPTION
The DG221B is a monolithic quad single-pole, single-throw
analog switch designed for precision switching applications in
communication, instrumentation and process control systems.
Featuring independent onboard latches and a common WR
pin, each DG221B can be memory mapped, and addressed as
a single data byte for simultaneous switching.
The DG221B combines low power and low on-resistance (60
W typical) while handling continuous currents up to 20 mA. An
epitaxial layer prevents latchup.
The device features true bidirectional performance in the on
condition.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Dual-In-Line and SOIC
IN1
D1
S1
V–
GND
S4
D4
IN4
1
2
3
4
5
6
7
8
16 IN2
15 D2
14 S2
13 V+
12 WR
11 S3
10 D3
9 IN3
Top View
Four Latchable SPST Switches per Package
TRUTH TABLE
INX WR
Switch
00
ON
10
OFF
Control data latched-in,
X switches on or off as selected
by last INX
X 1 Maintains previous state
Logic “0” v 0.8 V
Logic “1” w 2.4 V
ORDERING INFORMATION
Temp Range
Package
Part Number
–40_C to 85_C
16-Pin Plastic DIP
16-Pin Narrow SOIC
DG221BDJ
DG221BDY
Document Number: 71616
S-03627—Rev. A, 23-Apr-01
www.vishay.com
1
1 page TEST CIRCUITS
Rg
Vg
3V
+15 V
V+
SD
IN
WR
V–
–15 V
New Product
DG221B
Viswwhwa.DyatSaSihleiceto4Un.cioxm
VO
CL
1000 pF
VO
INX OFF
DVO
ON OFF
DVO = measured voltage error due to charge injection
The charge injection in coulombs is Q = CL x DVO
FIGURE 5. Charge Injection
+15 V
C
VS
Rg = 50 W
2.4 V
V+
SD
IN
GND WR V–
C
VO
RL
–15 V
Off Isolation = 20 log
C = RF bypass
VS
VO
FIGURE 6. Off Isolation
+15 V
C
VS
Rg = 50 W
0V
NC
0V
V+
S1 D1
IN1
S2 D2
IN2
GND WR V–
C
50 W
VO
RL
–15 V
XTALK Isolation = 20 log
C = RF bypass
VS
VO
FIGURE 7. Channel-to-Channel Crosstalk
APPLICATION HINTSa
V+
Positive Supply
Voltage
(V)
V–
Negative Supply
Voltage
(V)
GND
(V)
WR
(V)
15 –15 0 2.4/0.8
10 –10 0 2.4/0.8
10 –5 0 2.4/0.8
Notes:
a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
Document Number: 71616
S-03627—Rev. A, 23-Apr-01
VIN
Logic Input
Voltage
VINH(min)/VINL(max)
(V)
2.4/0.8
2.4/0.8
2.4/0.8
VS or VD
Analog Voltage
Range
(V)
–15 to 15
–10 to 10
–5 to 10
www.vishay.com
5
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet DG221B.PDF ] |
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