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PDF PCA9543B Data sheet ( Hoja de datos )
| Número de pieza | PCA9543B | |
| Descripción | 2-channel I2C-bus switch | |
| Fabricantes | NXP Semiconductors | |
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PCA9543A/43B/43C
www.DataSheet4U.com
2-channel I2C-bus switch with interrupt logic and reset
Rev. 05 — 17 November 2008
Product data sheet
1. General description
The PCA9543A/43B/43C is a bidirectional translating switch, controlled by the I2C-bus.
The SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any
individual SCx/SDx channels or combination of channels can be selected, determined by
the contents of the programmable control register. Two interrupt inputs, INT0 and INT1,
one for each of the downstream pairs, are provided. One interrupt output, INT, which acts
as an AND of the two interrupt inputs, is provided.
An active LOW reset input allows the PCA9543X to recover from a situation where one of
the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the
I2C-bus state machine and causes all the channels to be deselected, as does the internal
power-on reset function.
The pass gates of the switches are constructed such that the VDD pin can be used to limit
the maximum high voltage which will be passed by the PCA9543X. This allows the use of
different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
The PCA9543A, PCA9543B and PCA9543C are identical except for the fixed portion of
the slave address.
2. Features
I 1-of-2 bidirectional translating switches
I I2C-bus interface logic; compatible with SMBus standards
I 2 active LOW interrupt inputs
I Active LOW interrupt output
I Active LOW reset input
I 2 address pins allowing up to 4 devices on the I2C-bus
I Alternate address versions A, B and C allow up to a total of 12 devices on the bus for
larger systems or to resolve address conflicts
I Channel selection via I2C-bus, in any combination
I Power-up with all switch channels deselected
I Low Ron switches
I Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
I No glitch on power-up
I Supports hot insertion
I Low standby current
I Operating power supply voltage range of 2.3 V to 5.5 V
1 page  
NXP Semiconductors
PCA9543wAww/.4Da3taSBhee/t44U.3coCm
2-channel I2C-bus switch with interrupt logic and reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9543A/43B/43C”.
6.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9543A is shown in Figure 4. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
1 1 1 0 0 A1 A0 R/W
fixed
hardware
selectable
002aab169
Fig 4. Slave address PCA9543A
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
The PCA9543B and PCA9543C are alternate address versions if needed for larger
systems or to resolve address conflicts. The data sheet will reference the PCA9543A, but
the PCA9543B and PCA9543C function identically except for the slave address.
1 1 1 1 0 A1 A0 R/W
fixed
hardware
selectable
002aab799
Fig 5. Slave address PCA9543B
0 1 1 0 0 A1 A0 R/W
fixed
hardware
selectable
002aab800
Fig 6. Slave address PCA9543C
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9543A, which will be stored in the control register. If multiple bytes are
received by the PCA9543A, it will save the last byte received. This register can be written
and read via the I2C-bus.
PCA9543A_43B_43C_5
Product data sheet
interrupt bits
(read only)
channel selection bits
(read/write)
76543210
X
X
INT INT
10
X
X B1 B0
channel 0
channel 1
INT0
INT1
002aab181
Fig 7. Control register
Rev. 05 — 17 November 2008
© NXP B.V. 2008. All rights reserved.
5 of 23
5 Page 
NXP Semiconductors
PCA9543wAww/.4Da3taSBhee/t44U.3coCm
2-channel I2C-bus switch with interrupt logic and reset
8. Application design-in information
VDD = 2.7 V to 5.5 V
SDA
SCL
I2C/SMBus master
VDD = 3.3 V
SDA
SCL
INT
SD0
SC0
INT0
RESET
PCA9543A
A1 SD1
A0 SC1
VSS INT1
002aab184
V = 2.7 V to 5.5 V
see note (1)
channel 0
V = 2.7 V to 5.5 V
see note (1)
channel 1
(1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a
pull-up resistor is required.
If the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a
pull-up resistor is not required.
The interrupt inputs should not be left floating.
Fig 15. Typical application
9. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
VSS (ground = 0 V).[1]
Symbol Parameter
Conditions
Min Max Unit
VDD supply voltage
−0.5 +7.0 V
VI input voltage
−0.5 +7.0 V
II input current
- ±20 mA
IO output current
- ±25 mA
IDD supply current
-
±100
mA
ISS ground supply current
-
±100
mA
Ptot total power dissipation
- 400 mW
Tstg storage temperature
−60
+150
°C
Tamb
ambient temperature
operating
−40 +85 °C
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125 °C.
PCA9543A_43B_43C_5
Product data sheet
Rev. 05 — 17 November 2008
© NXP B.V. 2008. All rights reserved.
11 of 23
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| PDF Descargar | [ Datasheet PCA9543B.PDF ] | |
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