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PDF PCA9542A Data sheet ( Hoja de datos )
| Número de pieza | PCA9542A | |
| Descripción | 2-channel I2C-bus multiplexer and interrupt logic | |
| Fabricantes | NXP Semiconductors | |
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PCA9542A
www.DataSheet4U.com
2-channel I2C-bus multiplexer and interrupt logic
Rev. 03 — 24 November 2008
Product data sheet
1. General description
The PCA9542A is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.
The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.
Only one SCx/SDx channel is selected at a time, determined by the contents of the
programmable control register. Two interrupt inputs, INT0 and INT1, one for each of the
SCx/SDx downstream pairs, are provided. One interrupt output, INT, which acts as an
AND of the two interrupt inputs, is provided.
A power-on reset function puts the registers in their default state and initializes the I2C-bus
state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the VDD pin can be used to
limit the maximum high voltage which will be passed by the PCA9542A. This allows the
use of different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features
I 1-of-2 bidirectional translating multiplexer
I I2C-bus interface logic; compatible with SMBus
I 2 active LOW interrupt inputs (INT0, INT1)
I Active LOW interrupt output (INT)
I 3 address pins allowing up to 8 devices on the I2C-bus
I Channel selection via I2C-bus
I Powers up with all multiplexer channels deselected
I Low Ron switches
I Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
I No glitch on power-up
I Supports hot insertion
I Low standby current
I Operating power supply voltage range of 2.3 V to 5.5 V
I 5 V tolerant inputs
I 0 Hz to 400 kHz clock frequency
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: SO14, TSSOP14
1 page  
NXP Semiconductors
PCA9542Awww.DataSheet4U.com
2-channel I2C-bus multiplexer and interrupt logic
Table 4. Control register: Write—channel selection; Read—channel status
D7 D6 INT1 INT0 D3 B2 B1 B0 Command
X X X X X 0 X X no channel selected
X X X X X 1 0 0 channel 0 enabled
X X X X X 1 0 1 channel 1 enabled
X X X X X 1 1 X no channel selected
0 0 0 0 0 0 0 0 no channel selected;
power-up default state
6.3 Interrupt handling
The PCA9542A provides 2 interrupt inputs, one for each channel and one open-drain
interrupt output. When an interrupt is generated by any device, it will be detected by the
PCA9542A and the interrupt output will be driven LOW. The channel need not be active
for detection of the interrupt. A bit is also set in the control byte.
Bits 5:4 of the control byte correspond to channel 1, channel 0 of the PCA9542A,
respectively. Therefore, if an interrupt is generated by any device connected to channel 1,
the state of the interrupt inputs is loaded into the control register when a read is
accomplished. Likewise, an interrupt on any device connected to channel 0 would cause
bit 4 of the control register to be set on the read. The master can then address the
PCA9542A and read the contents of the control byte to determine which channel contains
the device generating the interrupt. The master can then reconfigure the PCA9542A to
select this channel, and locate the device generating the interrupt and clear it.
It should be noted that more than one device can be providing an interrupt on a channel,
so it is up to the master to ensure that all devices on a channel are interrogated for an
interrupt.
The interrupt inputs may be used as general purpose inputs if the interrupt function is not
required.
If unused, interrupt input(s) must be connected to VDD through a pull-up resistor.
Table 5. Control register read — interrupt
D7 D6 INT1 INT0 D3 B2 B1 B0 Command
0 no interrupt on channel 0
00X
XXXX
1 interrupt on channel 0
0 no interrupt on channel 1
00
XXXXX
1 interrupt on channel 1
Remark: The two interrupts can be active at the same time.
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9542A in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9542A registers and I2C-bus state machine are initialized to their default
states (all zeroes), causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V to reset the device.
PCA9542A_3
Product data sheet
Rev. 03 — 24 November 2008
© NXP B.V. 2008. All rights reserved.
5 of 22
5 Page 
NXP Semiconductors
PCA9542Awww.DataSheet4U.com
2-channel I2C-bus multiplexer and interrupt logic
10. Static characteristics
Table 7. Static characteristics
VDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
See Table 8 for VDD = 4.5 V to 5.5 V.[1]
Symbol Parameter
Conditions
Min
Supply
VDD supply voltage
IDD supply current
Istb standby current
VPOR
power-on reset voltage
Input SCL; input/output SDA
operating mode; VDD = 3.6 V;
no load; VI = VDD or VSS;
fSCL = 100 kHz
standby mode; VDD = 3.6 V; no load;
VI = VDD or VSS; fSCL = 0 kHz
no load; VI = VDD or VSS
2.3
-
-
[2] -
VIL LOW-level input voltage
VIH HIGH-level input voltage
IOL LOW-level output current
IL leakage current
Ci input capacitance
Select inputs A0, A1, A2, INT0, INT1
VOL = 0.4 V
VOL = 0.6 V
VI = VDD or VSS
VI = VSS
−0.5
0.7VDD
3
6
−1
-
VIL LOW-level input voltage
VIH HIGH-level input voltage
ILI input leakage current
Ci input capacitance
Pass gate
VI = VDD or VSS
VI = VSS
−0.5
0.7VDD
−1
-
Ron ON-state resistance
Vo(sw)
switch output voltage
IL leakage current
Cio input/output capacitance
INT output
VDD = 3.0 V to 3.6 V; VO = 0.4 V;
IO = 15 mA
VDD = 2.3 V to 2.7 V; VO = 0.4 V;
IO = 10 mA
Vi(sw) = VDD = 3.3 V; Io(sw) = −100 µA
Vi(sw) = VDD = 3.0 V to 3.6 V;
Io(sw) = −100 µA
Vi(sw) = VDD = 2.5 V; Io(sw) = −100 µA
Vi(sw) = VDD = 2.3 V to 2.7 V;
Io(sw) = −100 µA
VI = VDD or VSS
VI = VSS
5
7
-
1.6
-
1.1
−1
-
IOL LOW-level output current VOL = 0.4 V
IOH HIGH-level output current
3
-
Typ
-
10
0.1
1.6
-
-
7
10
-
9
-
-
-
1.6
11
16
1.9
-
1.5
-
-
3
-
-
[1] For operation between published voltage ranges, refer to worst case parameter in both ranges.
[2] VDD must be lowered to 0.2 V in order to reset part.
Max Unit
3.6 V
30 µA
1 µA
2.1 V
+0.3VDD
6
-
-
+1
10
V
V
mA
mA
µA
pF
+0.3VDD
VDD + 0.5
+1
3
V
V
µA
pF
30 Ω
55 Ω
-V
2.8 V
-V
2.0 V
+1 µA
5 pF
- mA
+10 µA
PCA9542A_3
Product data sheet
Rev. 03 — 24 November 2008
© NXP B.V. 2008. All rights reserved.
11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet PCA9542A.PDF ] | |
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