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CAT5261 Schematic ( PDF Datasheet ) - Catalyst Semiconductor

Teilenummer CAT5261
Beschreibung Dual Digitally Programmable Potentiometers
Hersteller Catalyst Semiconductor
Logo Catalyst Semiconductor Logo 




Gesamt 15 Seiten
CAT5261 Datasheet, Funktion
CAT5261www.DataSheet4U.com
Dual Digitally Programmable Potentiometers
(DPP™) with 256 Taps and SPI Interface
FEATURES
„ Two linear-taper digitally programmable
potentiometers
„ 256 resistor taps per potentiometer
„ End to end resistance 50kor 100k
„ Potentiometer control and memory access via
SPI interface
„ Low wiper resistance, typically 100
„ Nonvolatile memory storage for up to four
wiper settings for each potentiometer
„ Automatic recall of saved wiper settings at
power up
„ 2.5 to 6.0 volt operation
„ Standby current less than 1µA
„ 1,000,000 nonvolatile WRITE cycles
„ 100 year nonvolatile memory data retention
„ 24-lead SOIC and 24-lead TSSOP
„ Industrial temperature range
„ Industrial temperature range
For Ordering Information details, see page 14.
DESCRIPTION
The CAT5261 is two Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 8 bytes of NVRAM memory. Each DPP consists of
a series of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the wiper
tap switches for each DPP. Associated with each wiper
control register are four 8-bit non-volatile memory data
registers (DR) used for storing up to four wiper settings.
Writing to the wiper control register or any of the non-
volatile data registers is via a SPI serial bus. On power-
up, the contents of the first data register (DR0) for each
of the potentiometers is automatically loaded into its
respective wiper control register.
The CAT5261 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C
industrial operating temperature range and offered in
a 24-lead SOIC and TSSOP package.
PIN CONFIGURATION
SOIC/TSSOP (W, Y)
SO 1
24 H¯¯O¯L¯D¯
A0 2
23 SCK
NC 3
22 NC
NC 4
21 NC
NC 5
20 NC
NC
6
CAT
5261
19
NC
VCC 7
18 GND
RL0 8
17 RW1
RH0 9
16 RH1
RW0 10
¯C¯S¯ 11
15 RL1
14 A1
¯W¯P¯ 12
13 SI
FUNCTIONAL DIAGRAM
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
RH0 RH1
WP
A0
A1
HOLD
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
RL0 RL1
RW0
RW1
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2122 Rev. E






CAT5261 Datasheet, Funktion
CAT5261
POWER UP TIMING (1)(2)
Symbol Parameter
tPUR Power-up to Read Operation
tPUW Power-up to Write Operation
www.DataSheet4U.com
Max
1
1
Units
ms
ms
XDCP TIMING
Symbol Parameter
tWRPO
tWRL
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
Min Max Units
5 10 µs
5 10 µs
WRITE CYCLE LIMITS
Symbol Parameter
tWR Write Cycle Time
RELIABILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Max
5
Units
ms
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
V
mA
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
Figure 1. Synchronous Data Timing
VIH
CS
SCK
VIL
tCSS
VIH
VIL
VIH
SI
VIL
tWH
tSU tH
VALID IN
VOH
SO
VOL
HI-Z
tCS
tCSH
tWL
ttFRII
tV
tHO
tDIS
HI-Z
Note: Dashed Line = mode (1, 1)
Doc. No. MD-2122 Rev. E
6 © Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

6 Page









CAT5261 pdf, datenblatt
CAT5261
PACKAGE OUTLINE DRAWINGS
SOIC 24-Lead 300mils (W)
be
PIN#1 IDENTIFICATION
TOP VIEW
D
A
SIDE VIEW
www.DataSheet4U.c
E1 E
SYMBOL
A
A1
A2
b
c
D
E
E1
e
h
L
θ
θ1
MIN
2.35
0.10
2.05
0.31
0.20
15.20
10.11
7.34
0.25
0.40
NOM
1.27 BSC
MAX
2.65
0.30
2.55
0.51
0.33
15.40
10.51
7.60
0.75
1.27
15°
A2
A1
hh
θ
L θ1
END VIEW
θ1
c
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC specification MS-013.
Doc. No. MD-2122 Rev. E
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

12 Page





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