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AD6636 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD6636
Beschreibung 150 MSPS Wideband Digital Down-Converter (DDC)
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD6636 Datasheet, Funktion
150 MSPS Wideband
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Digital Down-Converter (DDC)
AD6636
FEATURES
4/6 independent wideband processing channels
Processes 6 wideband carriers (UMTS, CDMA2000)
4 single-ended or 2 LVDS parallel input ports
(16 linear bit plus 3-bit exponent) running at 150 MHz
Supports 300 MSPS input using external interface logic
3 16-bit parallel output ports operating up to 200 MHz
Real or complex input ports
Quadrature correction and dc correction for complex inputs
Supports output rate up to 34 MSPS per channel
RMS/peak power monitoring of input ports
Programmable attenuator control for external gain ranging
3 programmable coefficient FIR filters per channel
2 decimating half-band filters per channel
6 programmable digital AGC loops with 96 dB range
Synchronous serial I/O operation (SPI®-, SPORT-compatible)
Supports 8-bit or 16-bit microport modes
3.3 V I/O, 1.8 V CMOS core
User-configurable built-in self-test (BIST) capability
JTAG boundary scan
APPLICATIONS
Multicarrier, multimode digital receivers
GSM, EDGE, PHS, UMTS, WCDMA, CDMA2000, TD-SCDMA
Micro and pico cell systems, software radios
Broadband data applications
Instrumentation and test equipment
Wireless local loop
In-building wireless telephony
FUNCTIONAL BLOCK DIAGRAM
CLKA
ADC A/AI
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
EXPA [2:0]
CLKB
ADC B/AQ
EXPB [2:0]
CLKC
ADC C/CI
CMOS
REAL
PORTS
A, B,
C,D
CMOS
EXPC [2:0] COMPLEX
PORTS
(AI, AQ)
CLKD (BI, BQ)
ADC D/CQ
EXPD [2:0]
______
RESET
SYNC [3:0]
LVDS
PORTS
AB, CD
PEAK/
RMS
MEAS.
I,Q
CORR.
NCO
NCO
NCO
NCO
NCO
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
CIC5
M = 1-32
FIR1
HB1
M = Byp, 2
FIR2
HB2
M = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
PA
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
AGC PB
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
PC
MRCF
DRCF
M = 1-16
CRCF
M = 1-16
LHB
L = Byp, 2
PLL CLOCK
MULTIPLIER
16-BIT
MICROPORT INTERFACE
SPORT/SPI INTERFACE
JTAG
NOTE: CHANNELS RENDERED AS
ARE AVAILABLE ONLY IN 6-CHANNEL PART
M = DECIMATION
L = INTERPOLATION
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD6636 Datasheet, Funktion
AD6636
GENERAL TIMING CHARACTERISTICS
Table 3. General Timing Characteristics1, 2
Parameter
CLK TIMING REQUIREMENTS
tCLK CLKx Period (x = A, B, C, D)
tCLKL CLKx Width Low (x = A, B, C, D)
tCLKH CLKx Width High (x = A, B, C, D)
tCLKSKEW CLKA to CLKx Skew (x = B, C, D)
INPUT WIDEBAND DATA TIMING REQUIREMENTS
tSI INx [15:0] to CLKx Setup Time (x = A, B, C, D)
tHI INx [15:0] to CLKx Hold Time (x = A, B, C, D)
tSEXP EXPx [2:0] to CLKx Setup Time (x = A, B, C, D)
tHEXP EXPx [2:0] to CLKx Hold Time (x = A, B, C, D)
tDEXP CLKx to EXPx[2:0] Delay (x = A, B, C, D)
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER)
tDPREQ
PCLK to Px REQ Delay (x = A, B, C)
tDPP PCLK to Px [15:0] Delay (x = A, B, C)
tDPIQ PCLK to Px IQ Delay (x = A, B, C)
tDPCH PCLK to Px CH[2:0] Delay (x = A, B, C)
tDPGAIN
PCLK to Px Gain Delay (x = A, B, C)
tSPA Px ACK to PCLK Setup Time (x = A, B, C)
tHPA Px ACK to PCLK Hold Time (x = A, B, C)
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE)
tPCLK PCLK Period
tPCLKL
PCLK Low Period
tPCLKH
PCLK High Period
tDPREQ
PCLK to Px REQ Delay (x = A, B, C)
tDPP PCLK to Px [15:0] Delay (x = A, B, C)
tDPIQ PCLK to Px IQ Delay (x = A, B, C)
tDPCH PCLK to Px CH[2:0] Delay (x = A, B, C)
tDPGAIN
PCLK to Px Gain Delay (x = A, B, C)
tSPA Px ACK to PCLK Setup Time (x = A, B, C)
tHPA Px ACK to PCLK Hold Time (x = A, B, C)
MISC PINS TIMING REQUIREMENTS
tRESET
RESET Width Low
tDIRP CPUCLK/SCLK to IRP Delay
tSS SYNC(0, 1, 2, 3) to CLKA Setup Time
tHS SYNC(0, 1, 2, 3) to CLKA Hold Time
www.DataSheet4U.com
Temp Test Level Min
Typ
Max Unit
Full I
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
6.66
1.71
1.70
tCLK − 1.3
0.5 × tCLK
0.5 × tCLK
0.75
1.13
3.37
1.11
5.98
ns
ns
ns
ns
10.74
ns
ns
ns
ns
ns
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
1.77
2.07
0.48
0.38
0.23
4.59
0.90
3.86 ns
5.29 ns
5.49 ns
5.35 ns
4.95 ns
ns
ns
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
Full IV
5.0 ns
1.7 0.5 × tPCLK
ns
0.7 0.5 × tPCLK
ns
4.72 8.87 ns
4.8 8.48 ns
4.83 10.94 ns
4.88 10.09 ns
5.08 11.49 ns
6.09 ns
1.0 ns
Full IV
Full V
Full IV
Full IV
30
7.5
0.87
0.67
ns
ns
ns
ns
1 All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.
2 CLOAD = 40 pF on all outputs, unless otherwise noted.
Rev. 0 | Page 6 of 72

6 Page









AD6636 pdf, datenblatt
AD6636
Name
Type
SERIAL PORT CONTROL
SCLK
Input
SDO Output
SDI2 Input
STFS Input
SRFS
Input
SCS Input
MSB_FIRST
Input
SMODE
Input
JTAG
TRST1
TCLK2
TMS1
TDO
TDI1
Input
Input
Input
Output
Input
Pin No.
R1
M6
N11
N4
P4
N5
R3
P5
B13
C12
C11
A13
D10
1 Pin with a pull-up resistor of nominal 70 kΩ.
2 Pin with a pull-down resistor of nominal 70 kΩ.
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Function
Serial Clock.
Serial Port Data Output.
Serial Port Data Input.
Serial Transmit Frame Sync.
Serial Receive Frame Sync.
Serial Chip Select.
Select MSB First into SDI Pin and MSB First Out of SDO Pin. Logic 0 = MSB first;
Logic 1 = LSB first.
Serial Mode Select. Pull high when serial port is used and low when microport is
used.
Test Reset Pin. Pull low when JTAG is not used.
Test Clock.
Test Mode Select.
Test Data Output. Three-stated when JTAG is in reset.
Test Data Input.
PIN LISTING FOR POWER, GROUND, DATA AND ADDRESS BUSES
Table 8.
Name
VDDCORE
VDDIO
GND
INA[0:15]
INB[0:15]
INC[0:15]
IND[0:15]
PA[0:15]
PB[0:15]
PC[0:15]
D[0:15]
A[0:7]
Pin No.
A9, G6, G11, H1, H6, H11, J6, J11, J16, K6, K11, T8
B2, B15, F7, F8, F9, F10, L7, L8, L9, L10, R2, R15
A1, A8, A16, E5, F6, F11, G7, G8, G9, G10, H7, H8, H9, H10, H16, J1, J7, J8, J9, J10, K7, K8, K9, K10, L6, L11, M5,
P7, T1, T9, T10, T15, T16
N3, P2, P1, N2, N1, M1, L2, K3, K2, J2, H2, G1, F1, F2, E1, E2
M4, L4, M3, L5, L3, M2, K4, K5, J4, J5, J3, H4, H3, G2, H5, G3
C3, C4, B3, A2, D6, C6, E7, D7, E8, D8, C8, E9, D9, C9, B10, E10
B1, E6, D5, C5, A3, B4, B5, A4, B6, C7, B7, A7, B8, B9, A10, A11
F16, H15, G16, J12, J15, J14, K16, J13, K15, K14, L16, M16, K12, L15, N16, K13
F13, E15, G14, G12, E13, E14, F12, F14, C14, D14, C16, A15, B16, D15, D13, C15
M14, N14, M13, L12, P14, N13, R14, M12, T14, R13, P13, P12, M11, T13, T12, N12
R10, N9, N8, T7, P9, M9, R9, T5, T6, P8, R7, R8, N7, M7, R6, M8
N11, R12, P11, R11, N10, M10, P10, T11
Rev. 0 | Page 12 of 72

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