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Teilenummer | EBE82AF4A1RA |
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Beschreibung | 8GB Registered DDR2 SDRAM DIMM | |
Hersteller | Elpida Memory | |
Logo | ||
Gesamt 30 Seiten PRELIMINARY DATA SHEET
www.DataSheet4U.com
8GB Registered DDR2 SDRAM DIMM
EBE82AF4A1RA (1024M words × 72 bits, 4 Ranks)
Specifications
• Density: 8GB
• Organization
⎯ 1024M words × 72 bits, 4 ranks
• Mounting 36 pieces of 2G bits DDR2 SDRAM with
DDP (FBGA)
⎯ DDP: 2 pieces of 1Gb chips sealed in one package
• Package: 240-pin socket type dual in line memory
module (DIMM)
⎯ PCB height: 30.0mm
⎯ Lead pitch: 1.0mm
⎯ Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 667Mbps/533Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
⎯ Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
⎯ TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E1166E10 (Ver. 1.0)
Date Published March 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2008
EBE82AF4A1RA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex vwawluwe .DaCtaomShmeeentt4sU.com
Address and command setup time
32 before clock (tIS)
0 0 1 0 0 0 0 0 20H
-6E
-5C 0 0 1 0 0 1 0 1 25H
Address and command hold time after
33 clock (tIH)
0 0 1 0 0 1 1 1 27H
-6E
-5C 0 0 1 1 0 1 1 1 37H
34 Data input setup time before clock (tDS) 0 0 0 1 0 0 0 0 10H
0.20ns*1
0.25ns*1
0.27ns*1
0.37ns*1
0.10ns*1
Data input hold time after clock (tDH)
35 0 0 0 1 0 1 1 1 17H
-6E
-5C 0 0 1 0 0 0 1 0 22H
36 Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
0.17ns*1
0.22ns*1
15ns*1
37
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
38
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
7.5ns*1
7.5ns*1
39 Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
TBD
40 Extension of Byte 41 and 42
41 Active command period (tRC)
0 0 0 0 0 1 1 0 06H
0 0 1 1 1 1 0 0 3CH
60ns*1
42
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1111
1 1 1 7FH
43
SDRAM tCK cycle max. (tCK max.)
1 0 0 0 0 0 0 0 80H
Dout to DQS skew
44
-6E
0 0 0 1 1 0 0 0 18H
-5C 0 0 0 1 1 1 1 0 1EH
Data hold skew (tQHS)
45
-6E
0 0 1 0 0 0 1 0 22H
-5C 0 0 1 0 1 0 0 0 28H
127.5ns*1
8ns*1
0.24ns*1
0.30ns*1
0.34ns*1
0.40ns*1
46 PLL relock time
0 0 0 0 1 1 1 1 0FH
15μs
47 to 61
0 0 0 0 0 0 0 0 00H
62 SPD Revision
0 0 0 1 0 0 1 0 12H
Rev. 1.2
63 Checksum for bytes 0 to 62
-6E
-5C
64 to 65 Manufacturer’s JEDEC ID code
0 1 0 0 0 1 0 0 44H
1 0 0 0 1 0 0 0 88H
0 1 1 1 1 1 1 1 7FH
Continuation
code
66 Manufacturer’s JEDEC ID code
1 1 1 1 1 1 1 0 FEH
Elpida Memory
67 to 71 Manufacturer’s JEDEC ID code
72 Manufacturing location
73 Module part number
0 0 0 0 0 0 0 0 00H
× × × × × × × × ××
0 1 0 0 0 1 0 1 45H
(ASCII-8bit
code)
E
74 Module part number
0 1 0 0 0 0 1 0 42H
B
75 Module part number
0 1 0 0 0 1 0 1 45H
E
76 Module part number
0 0 1 1 1 0 0 0 38H
8
77 Module part number
0 0 1 1 0 0 1 0 32H
2
78 Module part number
0 1 0 0 0 0 0 1 41H
A
79 Module part number
0 1 0 0 0 1 1 0 46H
F
80 Module part number
0 0 1 1 0 1 0 0 34H
4
Preliminary Data Sheet E1166E10 (Ver. 1.0)
6
6 Page EBE82AF4A1RA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Symbol Grade
max.
Unit Test condition
Operating current
(ACT-PRE)
IDD0
Operating current
(ACT-READ-PRE)
IDD1
Precharge power-down
standby current
IDD2P
Precharge quiet standby
current
IDD2Q
Idle standby current
IDD2N
TBD
TBD
TBD
TBD
TBD
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down
standby current
IDD3P-F
IDD3P-S
TBD
TBD
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address
bus inputs are STABLE;
mA Data bus inputs are
FLOATING
Slow PDN Exit
MRS(12) = 1
Active standby current
IDD3N
Operating current
(Burst read operating)
IDD4R
Operating current
(Burst write operating)
IDD4W
TBD
TBD
TBD
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Preliminary Data Sheet E1166E10 (Ver. 1.0)
12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ EBE82AF4A1RA Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
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