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Teilenummer | EBE52UD6AJUA |
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Beschreibung | 512MB DDR2 SDRAM SO-DIMM | |
Hersteller | Elpida Memory | |
Logo | ||
Gesamt 28 Seiten DATA SHEET
www.DataSheet4U.com
512MB DDR2 SDRAM SO-DIMM
EBE52UD6AJUA (64M words × 64 bits, 2 Ranks)
Specifications
• Density: 512MB
• Organization
64M words × 64 bits, 2 ranks
• Mounting 8 pieces of 512M bits DDR2 SDRAM
sealed in FBGA
• Package: 200-pin socket type small outline dual in
line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• Four internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E1084E30 (Ver. 3.0)
Date Published April 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2008
EBE52UD6AJUA
www.DataSheet4U.com
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Maximum data access time (tAC) from
26 clock at CL = X − 2
0 1 1 0 0 0 0 0 60H
-8E, -6E (CL = 3)
-8G (CL = 4)
0 1 0 1 0 0 0 0 50H
27
Minimum row precharge time (tRP)
-8E
0 0 1 1 0 0 1 0 32H
-8G, -6E
0 0 1 1 1 1 0 0 3CH
28
Minimum row active to row active delay
(tRRD)
0
0
1
0
1
0
0
0
28H
29
Minimum /RAS to /CAS delay (tRCD)
-8E
0 0 1 1 0 0 1 0 32H
-8G, -6E
0 0 1 1 1 1 0 0 3CH
30
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
31 Module rank density
0 1 0 0 0 0 0 0 40H
Address and command setup time
32 before clock (tIS)
0 0 0 1 0 1 1 1 17H
-8E, -8G
-6E 0 0 1 0 0 0 0 0 20H
Address and command hold time after
33 clock (tIH)
0 0 1 0 0 1 0 1 25H
-8E, -8G
-6E 0 0 1 0 0 1 1 1 27H
34
Data input setup time before clock (tDS)
-8E, -8G
0
0
0
0
0
1
0
1
05H
-6E 0 0 0 1 0 0 0 0 10H
35
Data input hold time after clock (tDH)
-8E, -8G
0 0 0 1 0 0 1 0 12H
-6E 0 0 0 1 0 1 1 1 17H
36 Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
37
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
38
Internal read to precharge command
delay (tRTP)
0 0 0 1 1 1 1 0 1EH
39 Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
40
Extension of Byte 41 and 42
-8E
0 0 1 1 0 0 0 0 30H
-8G, -6E
0 0 0 0 0 0 0 0 00H
41
Active command period (tRC)
-8E
0 0 1 1 1 0 0 1 39H
-8G, -6E
0 0 1 1 1 1 0 0 3CH
42
Auto refresh to active/
Auto refresh command cycle (tRFC)
0 1 1 0 1 0 0 1 69H
43
SDRAM tCK cycle max. (tCK max.)
1 0 0 0 0 0 0 0 80H
44
Dout to DQS skew
-8E, -8G
0 0 0 1 0 1 0 0 14H
-6E 0 0 0 1 1 0 0 0 18H
45
Data hold skew (tQHS)
-8E, -8G
0 0 0 1 1 1 1 0 1EH
-6E 0 0 1 0 0 0 1 0 22H
Comments
0.6ns*1
0.5ns*1
12.5ns
15ns
10ns
12.5ns
15ns
45ns
256M bytes
0.17ns*1
0.20ns*1
0.25ns*1
0.27ns*1
0.05ns*1
0.10ns*1
0.12ns*1
0.17ns*1
15ns*1
7.5ns*1
7.5ns*1
TBD
Undefined
57.5ns*1
60ns*1
105ns*1
8ns*1
0.20ns*1
0.24ns*1
0.30ns*1
0.34ns*1
46 PLL relock time
0 0 0 0 0 0 0 0 00H
Undefined
47 to 61
0 0 0 0 0 0 0 0 00H
Undefined
Data Sheet E1084E30 (Ver. 3.0)
6
6 Page EBE52UD6AJUA
Parameter
Symbol Grade max.
Unit Test condition
www.DataSheet4U.com
Auto-refresh current
(Another rank is in IDD2P)
IDD5
Auto-refresh current
(Another rank is in IDD3N)
IDD5
-8E, -8G 460
-6E 440
-8E, -8G 580
-6E 540
mA
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
mA
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-refresh current
IDD6
Self Refresh Mode;
CK and /CK at 0V;
48 mA CKE ≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating current
(Bank interleaving)
IDD7
(Another rank is in IDD2P)
Operating current
(Bank interleaving)
IDD7
(Another rank is in IDD3N)
-8E, -8G 1000
-6E 960
-8E, -8G 1120
-6E 1060
all bank interleaving reads, IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1 × tCK (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all
combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤VIL (AC) (max.)
H is defined as VIN ≥VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-800
DDR2-800
Parameter
CL (IDD)
5-5-5
5
6-6-6
6
tRCD (IDD)
12.5 15
tRC (IDD)
57.5 60
tRRD (IDD) 10 10
tCK (IDD)
2.5 2.5
tRAS (min.)(IDD)
45
45
tRAS (max.)(IDD)
70000
70000
tRP (IDD)
12.5 15
tRFC (IDD)
105 105
DDR2-667
5-5-5
5
15
60
10
3
45
70000
15
105
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet E1084E30 (Ver. 3.0)
12
12 Page | ||
Seiten | Gesamt 28 Seiten | |
PDF Download | [ EBE52UD6AJUA Schematic.PDF ] |
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