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PDF EBE52UD6AFSA Data sheet ( Hoja de datos )
| Número de pieza | EBE52UD6AFSA | |
| Descripción | 512MB DDR2 SDRAM SO-DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
www.DataSheet4U.com
512MB DDR2 SDRAM SO-DIMM
EBE52UD6AFSA (64M words × 64 bits, 2 Ranks)
Description
The EBE52UD6AFSA is 64M words × 64 bits, 2 ranks
DDR2 SDRAM Small Outline Dual In-line Memory
Module, mounting 8 pieces of 512M bits DDR2
SDRAM sealed in FBGA (µBGA) package. Read and
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 4 bits prefetch-pipelined architecture.
Data strobe (DQS and /DQS) both for read and write
are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without
utilizing surface mount technology. Decoupling
capacitors are mounted beside each FBGA (µBGA) on
the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
• 200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 667Mbps/533Mbps/400Mbps (max.)
• SSTL_18 compatible I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
(Components)
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation.
Document No. E0722E30 (Ver. 3.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
1 page  
EBE52UD6AFSA
Serial PD Matrix
www.DataSheet4U.com
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
2 Memory type
0 0 0 0 1 0 0 0 08H
3 Number of row address
0 0 0 0 1 1 0 1 0DH
4 Number of column address
0 0 0 0 1 0 1 0 0AH
5 Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
6 Module data width
0 1 0 0 0 0 0 0 40H
7 Module data width continuation 0 0 0 0 0 0 0 0 00H
8 Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
9
DDR SDRAM cycle time, CL = 5
-6E
0 0 1 1 0 0 0 0 30H
-5C 0 0 1 1 1 1 0 1 3DH
-4A 0 1 0 1 0 0 0 0 50H
10
SDRAM access from clock (tAC)
-6E
0 1 0 0 0 1 0 1 45H
-5C 0 1 0 1 0 0 0 0 50H
-4A 0 1 1 0 0 0 0 0 60H
11 DIMM configuration type
0 0 0 0 0 0 0 0 00H
12 Refresh rate/type
1 0 0 0 0 0 1 0 82H
13 Primary SDRAM width
0 0 0 1 0 0 0 0 10H
14 Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
15 Reserved
0 0 0 0 0 0 0 0 00H
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
18
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
19
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
20 DIMM type information
0 0 0 0 0 1 0 0 04H
21 SDRAM module attributes
0 0 0 0 0 0 0 0 00H
22
SDRAM device attributes: General
-6E
0 0 0 0 0 0 1 1 03H
-5C, -4A
0 0 0 0 0 0 0 1 01H
23
Minimum clock cycle time at CL = 4
-6E, -5C
0 0 1 1 1 1 0 1 3DH
-4A 0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC) from
24 clock at CL = 4
0 1 0 1 0 0 0 0 50H
-6E, -5C
-4A 0 1 1 0 0 0 0 0 60H
Comments
128 bytes
256 bytes
DDR2 SDRAM
13
10
2
64
0
SSTL 1.8V
3.0ns*1
3.75ns*1
5.0ns*1
0.45ns*1
0.5ns*1
0.6ns*1
None.
7.8µs
× 16
None.
0
4,8
4
3, 4, 5
3.80mm max.
SO-DIMM
Normal
Weak Driver
50Ω ODT Support
Weak Driver
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
Data Sheet E0722E30 (Ver. 3.0)
5
5 Page 
EBE52UD6AFSA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V)
www.DataSheet4U.com
Parameter
Symbol
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD2P)
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD3N)
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD2P)
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD3N)
Grade
-6E
-5C
-4A
-6E
-5C
-4A
-6E
-5C
-4A
-6E
-5C
-4A
Precharge power-down
standby current
IDD2P
-6E
-5C
-4A
max.
520
480
452
720
640
620
600
560
532
800
720
700
80
80
64
Precharge quiet standby
current
IDD2Q
-6E
-5C
-4A
240
200
160
Idle standby current
Active power-down
standby current
IDD2N
-6E
-5C
-4A
IDD3P-F
IDD3P-S
-6E
-5C
-4A
-6E
-5C
-4A
280
240
200
280
240
240
160
160
160
Unit Test condition
mA
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
mA Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address
mA
bus inputs are STABLE; Slow PDN Exit
Data bus inputs are
MRS(12) = 1
FLOATING
all banks open;
-6E 480
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
Active standby current
IDD3N -5C
400
mA CKE is H, /CS is H between valid commands;
-4A 400
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD2P)
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD3N)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD2P)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD3N)
-6E
-5C
-4A
-6E
-5C
-4A
-6E
-5C
-4A
-6E
-5C
-4A
960 all banks open, continuous burst reads, IOUT = 0mA;
820 mA BL = 4, CL = CL(IDD), AL = 0;
672 tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
1160
CKE is H, /CS is H between valid commands;
980 mA Address bus inputs are SWITCHING;
840 Data pattern is same as IDD4W
960 all banks open, continuous burst writes;
820 mA BL = 4, CL = CL(IDD), AL = 0;
672 tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
1160
Address bus inputs are SWITCHING;
980 mA Data bus inputs are SWITCHING
840
Data Sheet E0722E30 (Ver. 3.0)
11
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| PDF Descargar | [ Datasheet EBE52UD6AFSA.PDF ] | |
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