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EBE52UC8AAFV Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBE52UC8AAFV
Beschreibung 512MB Unbuffered DDR2 SDRAM HYPER DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 22 Seiten
EBE52UC8AAFV Datasheet, Funktion
PRELIMINARY DATA SHEET
www.DataSheet4U.com
512MB Unbuffered DDR2 SDRAM
HYPER DIMM
EBE52UC8AAFV (64M words × 64 bits, 2 Ranks)
Description
The EBE52UC8AAFV is 64M words × 64 bits, 2 ranks
DDR2 SDRAM unbuffered module, mounting 16 pieces
of 256M bits DDR2 SDRAM sealed in FBGA package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 4 bits prefetch-pipelined
architecture. Data strobe (DQS and /DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each FBGA
on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free
1.8V power supply
Data rate: 700Mbps/667Mbps/600Mbps (max.)
1.8V (SSTL_18 compatible) I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
(Component)
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8µs average periodic refresh interval
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
Document No. E0526E12 (Ver. 1.2) This product became EOL in April, 2005.
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2006






EBE52UC8AAFV Datasheet, Funktion
EBE52UC8AAFV
www.DataSheet4U.com
Byte No.
36
37
38
39
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
Comments
15ns*1
7.5ns*1
7.5ns*1
TBD
40 Extension of Byte 41 and 42
0 0 0 0 0 0 0 0 00H
41 Active command period (tRC)
0 0 1 1 1 1 0 0 3CH
42
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1
0
0
1
0
1
1
4BH
43 SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H
44 Dout to DQS skew
0 0 0 1 1 1 1 0 1EH
45 Data hold skew (tQHS)
0 0 1 0 1 0 0 0 28H
46 PLL relock time
0 0 0 0 0 0 0 0 00H
47 to 61
0 0 0 0 0 0 0 0 00H
Undefined
60ns*1
75ns*1
8ns*1
0.30ns*1
0.40ns*1
Undefined
62 SPD Revision
0 0 0 1 0 0 0 0 10H
Rev. 1.0
63 Checksum for bytes 0 to 62
64 to 65 Manufacturer’s JEDEC ID code
66 Manufacturer’s JEDEC ID code
1 0 0 0 0 0 1 1 83H
0 1 1 1 1 1 1 1 7FH
1 1 1 1 1 1 1 0 FEH
Continuation
code
Elpida Memory
67 to 71 Manufacturer’s JEDEC ID code
72 Manufacturing location
73 Module part number
0 0 0 0 0 0 0 0 00H
× × × × × × × × ××
0 1 0 0 0 1 0 1 45H
(ASCII-8bit
code)
E
74 Module part number
0 1 0 0 0 0 1 0 42H
B
75 Module part number
76 Module part number
0 1 0 0 0 1 0 1 45H
0 0 1 1 0 1 0 1 35H
E
5
77 Module part number
78 Module part number
79 Module part number
0 0 1 1 0 0 1 0 32H
0 1 0 1 0 1 0 1 55H
0 1 0 0 0 0 1 1 43H
2
U
C
80 Module part number
0 0 1 1 1 0 0 0 38H
8
81 Module part number
82 Module part number
0 1 0 0 0 0 0 1 41H
0 1 0 0 0 0 0 1 41H
A
A
83 Module part number
84 Module part number
85 Module part number
Module part number
86
-DF
-BE
-AE
Module part number
87 -DF
-BE
0 1 0 0 0 1 1 0 46H
0 1 0 1 0 1 1 0 56H
0 0 1 0 1 1 0 1 2DH
0 1 0 0 0 1 0 0 44H
0 1 0 0 0 0 1 0 42H
0 1 0 0 0 0 0 1 41H
0 1 0 0 0 1 1 0 46H
0 1 0 0 0 1 0 1 45H
F
V
D
B
A
F
E
-AE
88 Module part number
0 1 0 0 0 1 0 1 45H
0 0 1 0 1 1 0 1 2DH
E
Preliminary Data Sheet E0526E12 (Ver. 1.2)
6

6 Page









EBE52UC8AAFV pdf, datenblatt
EBE52UC8AAFV
www.DataSheet4U.com
Parameter
Symbol Grade
Auto-refresh current
(Another rank is in IDD2P)
IDD5
-DF
-BE
-AE
Auto-refresh current
(Another rank is in IDD3N)
IDD5
-DF
-BE
-AE
max.
2256
2256
2168
2840
2800
2680
Self-refresh current
IDD6
96
Unit Test condition
mA tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
mA Data bus inputs are SWITCHING
Self Refresh Mode;
CK and /CK at 0V;
mA CKE 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating current
(Bank interleaving)
IDD7
(Another rank is in IDD2P)
Operating current
(Bank interleaving)
IDD7
(Another rank is in IDD3N)
-DF
-BE
-AE
-DF
-BE
-AE
2816
2816
2728
3400
3360
3240
all bank interleaving reads, IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1 × tCK (IDD); See Notes 7;
CKE is H, CS is H between valid commands;
mA Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN VIL (AC) (max.)
H is defined as VIN VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
7. In case of -DF (DDR2-700), tRCD must be 2 × tCK (IDD) and AL must be 4 × tCK (IDD) because AL = 5 is
not supported in this device.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-700
DDR2-667
Parameter
CL(IDD)
5-6-6
5
5-5-5
5
tRCD(IDD)
15
15
tRC(IDD)
67.5
60
tRRD(IDD)
7.5
7.5
tCK(IDD)
2.85
3
tRAS(min.)(IDD)
50
45
tRAS(max.)(IDD)
70000
70000
tRP(IDD)
15
15
tRFC(IDD)
85
75
DDR2-600
5-5-5
5
15
65
7.5
3.3
47.5
70000
15
80
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Data Sheet E0526E12 (Ver. 1.2)
12

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