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EBE51UD8ABFV Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBE51UD8ABFV
Beschreibung 512MB Unbuffered DDR2 SDRAM HYPER DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 22 Seiten
EBE51UD8ABFV Datasheet, Funktion
PRELIMINARY DATA SHEET
www.DataSheet4U.com
512MB Unbuffered DDR2 SDRAM
HYPER DIMM
EBE51UD8ABFV (64M words × 64 bits, 1 Rank)
Description
The EBE51UD8ABFV is 64M words × 64 bits, 1 rank
DDR2 SDRAM unbuffered module, mounting 8 pieces
of 512M bits DDR2 SDRAM sealed in FBGA package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 4 bits prefetch-pipelined
architecture. Data strobe (DQS and /DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each FBGA
on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free
1.85V power supply
Data rate: 667Mbps/600Mbps (max.)
SSTL_18 compatible I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
(components)
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8µs average periodic refresh interval
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
Document No. E0528E12 (Ver. 1.2) This product became EOL in April, 2005.
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2006






EBE51UD8ABFV Datasheet, Funktion
EBE51UD8ABFV
Byte No.
37
38
39
40
41
42
43
44
45
46
47 to 61
62
63
64 to 65
66
67 to 71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
www.DataSheet4U.com
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
Comments
7.5ns*1
7.5ns*1
TBD
Extension of Byte 41 and 42
0 0 0 0 0 0 0 0 00H
Active command period (tRC)
0 0 1 1 1 1 0 0 3CH
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1
1
0
1
0
0
1
69H
SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H
Dout to DQS skew
0 0 0 1 1 1 1 0 1EH
Data hold skew (tQHS)
0 0 1 0 1 0 0 0 28H
Undefined
60ns*1
105ns*1
8ns*1
0.30ns*1
0.40ns*1
PLL relock time
0 0 0 0 0 0 0 0 00H
Undefined
0 0 0 0 0 0 0 0 00H
SPD Revision
0 0 0 1 0 0 0 0 10H
Rev. 1.0
Checksum for bytes 0 to 62
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
1 1 1 0 0 0 0 1 E1H
0 1 1 1 1 1 1 1 7FH
1 1 1 1 1 1 1 0 FEH
Continuation
code
Elpida Memory
Manufacturer’s JEDEC ID code
Manufacturing location
Module part number
0 0 0 0 0 0 0 0 00H
× × × × × × × × ××
0 1 0 0 0 1 0 1 45H
(ASCII-8bit
code)
E
Module part number
0 1 0 0 0 0 1 0 42H
B
Module part number
0 1 0 0 0 1 0 1 45H
E
Module part number
0 0 1 1 0 1 0 1 35H
5
Module part number
0 0 1 1 0 0 0 1 31H
1
Module part number
0 1 0 1 0 1 0 1 55H
U
Module part number
0 1 0 0 0 1 0 0 44H
D
Module part number
0 0 1 1 1 0 0 0 38H
8
Module part number
0 1 0 0 0 0 0 1 41H
A
Module part number
0 1 0 0 0 0 1 0 42H
B
Module part number
0 1 0 0 0 1 1 0 46H
F
Module part number
0 1 0 1 0 1 1 0 56H
V
Module part number
Module part number
-BE
-AE
Module part number
-BE
-AE
0 0 1 0 1 1 0 1 2DH
0 1 0 0 0 0 1 0 42H
0 1 0 0 0 0 0 1 41H
0 1 0 0 0 1 0 1 45H
0 1 0 0 0 1 0 1 45H
B
A
E
E
Module part number
0 0 1 0 1 1 0 1 2DH
Module part number
0 1 0 0 0 1 0 1 45H
E
Module part number
0 0 1 0 0 0 0 0 20H
(Space)
Revision code
0 0 1 1 0 0 0 0 30H
Initial
Revision code
0 0 1 0 0 0 0 0 20H
(Space)
Preliminary Data Sheet E0528E12 (Ver. 1.2)
6

6 Page









EBE51UD8ABFV pdf, datenblatt
EBE51UD8ABFV
www.DataSheet4U.com
Parameter
Symbol Grade
max.
Unit Test condition
Auto-refresh current
IDD5
-BE
-AE
2160
2080
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-refresh current
IDD6
Self Refresh Mode;
CK and /CK at 0V;
48 mA CKE 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating current
(Bank interleaving)
IDD7
-BE
-AE
2720
2640
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
mA tRCD = 1 × tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN VIL (AC) (max.)
H is defined as VIN VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667
DDR2-600
Parameter
5-5-5
5-5-5
CL(IDD)
5
5
tRCD(IDD)
15
15
tRC(IDD)
60
65
tRRD(IDD)
7.5
7.5
tCK(IDD)
3
3.3
tRAS(min.)(IDD)
45
47.5
tRAS(max.)(IDD)
70000
70000
tRP(IDD)
15
15
tRFC(IDD)
105
105
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Data Sheet E0528E12 (Ver. 1.2)
12

12 Page





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