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EBE42FE8ACWR Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBE42FE8ACWR
Beschreibung 4GB Fully Buffered DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 22 Seiten
EBE42FE8ACWR Datasheet, Funktion
DATA SHEET
www.DataSheet4U.com
4GB Fully Buffered DIMM
EBE42FE8ACWR
Specifications
Density: 4GB
Organization
512M words × 72 bits, 4 ranks
Mounting 36 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
Package
240-pin fully buffered, socket type dual in line
memory module (FB-DIMM)
PCB height: 30.35mm
Lead pitch: 1.00mm
Advanced Memory Buffer (AMB): 655-ball FCBGA
Lead-free (RoHS compliant)
Power supply
DDR2 SDRAM: VDD = 1.8V ± 0.1V
AMB: VCC = 1.5V +0.075V/ 0.045V
Data rate: 667Mbps (max.)
Eight internal banks for concurrent operation
(components)
Interface: SSTL_18
Burst lengths (BL): 4, 8
/CAS Latency (CL): 3, 4, 5
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
JEDEC standard Raw Card AE Design
Industry Standard Advanced Memory Buffer (AMB)
High-speed differential point-to-point link interface at
1.5V (JEDEC spec)
14 north-bound (NB) high speed serial lanes
10 south-bound (SB) high speed serial lanes
Various features/modes:
MemBIST and IBIST test functions
Transparent mode and direct access mode for
DRAM testing
Interface for a thermal sensor and status indicator
Channel error detection and reporting
Automatic DDR2 SDRAM bus and channel
calibration
SPD (serial presence detect) with 1piece of 256 byte
serial EEPROM
Note: Warranty void if removed DIMM heat
spreader.
Performance
System clock
frequency
167MHz
FB-DIMM
Speed grade
PC2-5300F
Peak channel
throughput
8.0GByte/s
DDR2 SDRAM
FB-DIMM link data rate
4.0Gbps
Speed Grade
DDR data rate
DDR2-667 (5-5-5) 667Mbps
Document No. E1386E10 (Ver. 1.0)
Date Published October 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008






EBE42FE8ACWR Datasheet, Funktion
EBE42FE8ACWR
High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces
www.DataSheet4U.com
The AMB supports one FB-DIMM channel consisting of two bidirectional link interfaces using high-speed differential
point-to-point electrical signaling. The southbound input link is 10 lanes wide and carries commands and write data
from the host memory controller or the adjacent DIMM in the host direction. The southbound output link forwards
this same data to the next FB-DIMM. The northbound input link is 14 lanes wide and carries read return data or
status information from the next FB-DIMM in the chain back towards the host. The northbound output link forwards
this information back towards the host and multiplexes in any read return data or status information that is generated
internally. Data and commands sent to the DRAMs travel southbound on 10 primary differential signal line pairs.
Data received from the DRAMs and status information travel northbound on 14 primary differential pairs. Data and
commands sent to the adjacent DIMM upstream are repeated and travel further southbound on 10 secondary
differential pairs. Data and status information received from the adjacent DIMM upstream travel further northbound
on 14 secondary differential pairs.
DDR2 Channel
The DDR2 channel on the AMB supports direct connection to DDR2 SDRAMs. The DDR2 channel supports four
ranks of eight banks with 15 row/column request, 64 data, and eight check-bit signals. There are two copies of
address and command signals excluding chip select, to support DIMM routing and electrical requirements. Four
transfer bursts are driven on the data and check-bit lines at 667MHz. Propagation delays between read data/check-
bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware state machines using
write/read trial and error. Hardware aligns the read data and check-bits to a single core clock. The AMB provides
four copies of the command clock phase references (CLK [3:0]) and write data/check-bit strobes (DQSs) for each
DRAM nibble.
SMBus Slave interface
The AMB supports an SMBus interface to allow system access to configuration register independent of the FB-DIMM
link. The AMB will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at
100kHz. SMBus access to the AMB may be a requirement to boot and to set link strength, frequency and other
parameters needed to insure robust configurations. It is also required for diagnostic support when the link is down.
The SMBus address straps located on the DIMM connector are used by the unique ID.
Data Sheet E1386E10 (Ver. 1.0)
6

6 Page









EBE42FE8ACWR pdf, datenblatt
EBE42FE8ACWR
Reference Clock Input Specifications*1
www.DataSheet4U.com
Parameter
Symbol
min. max.
Units Notes
Reference clock frequency@ 4.0 Gb/s
(nominal 166.67MHz)
fRefclk-4.0
158.33
166.75
MHz 2, 3, 4
Single-ended maximum voltage
Vmax
1.15 V 5, 7
Single-ended minimum voltage
Vmin
0.3
V 5, 8
Differential voltage high
VRefclk-diff-ih
150
mV 6
Differential voltage low
VRefclk-diff-il
150
mV 6
Absolute crossing point
VCross
250 550
mV 5, 9, 10
VCross variation
VCross-delta
140
mV 5, 9, 11
AC common mode
VSCK-cm-acp-p
225
mV 12
Rising and falling edge rates
% Mismatch between rise and fall edge
rates
ERRefclk-diff-Rise,
ERRefclk-diff-Fall
ERRefclk-Match
0.6
4.0
20
V/ns
%
6, 13
6, 14
Duty cycle of reference clock
TRefclk-Dutycycle 40
60
%6
Ringback voltage threshold
VRB-diff
100
100
mV 6, 15
Allowed time before ringback
TStable
500
ps 6, 15
Clock leakage current
II_CK
10 10
µA 16, 17
Clock input capacitance
CI_CK
0.5 2.0
pF 17
Clock input capacitance delta
CI_CK ()
0.25
0.25
Difference between
pF RefClk and RefClk#
input capacitance
Transport delay
TD
NSAMPLE
1012
5
ns 18, 19
periods 20
Reference clock jitter (rms), filtered
TREF-JITTER-RMS
3.0
ps 21, 22
Reference clock jitter (peak-to-peak) due
to spectrum clocking effects
TREF-SSCp-p
30
ps
Reference clock jitter difference between TREF-JITTER-
adjacent AMB
DELTA
0.75
ps 23
Notes: 1. For details, refer to the JEDEC specification “FB-DIMM High Speed Differential PTP Link at 1.5V”.
2. The nominal reference clock frequency is determined by the data frequency of the link divided by 2 times
the fixed PLL multiplication factor for the FB-DIMM channel (6:1). fdata = 2000MHz for a 4.0Gbps FB-
DIMM channel and so on.
3. Measured with SSC disabled. Enabling SSC will reduce the reference clock frequency.
4. Not all FB-DIMM agents will support all frequencies; compliance to the frequency specifications is only
required for those data rates that are supported by the device under test.
5. Measurement taken from single-ended waveform.
6. Measurement taken from differential waveform.
7. Defined as the maximum instantaneous voltage including overshoot.
8. Defined as the minimum instantaneous voltage including undershoot.
9. Measured at the crossing point where the instantaneous voltage value of the rising edge of REFCLK+
equals the falling edge of REFCLK-.
10. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing. Refers to all crossing points for this measurement.
11. Defined as the total variation of all crossing voltages of rising REFCLK+ and falling REFCLK-. This is the
maximum allowed variance in for any particular system.
12. The majority of the reference clock AC common mode occurs at high frequency (i.e., the reference clock
frequency).
Data Sheet E1386E10 (Ver. 1.0)
12

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