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PDF EBE42AE8ACFA Data sheet ( Hoja de datos )
| Número de pieza | EBE42AE8ACFA | |
| Descripción | 4GB Registered DDR2 SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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DATA SHEET
www.DataSheet4U.com
4GB Registered DDR2 SDRAM DIMM
EBE42AE8ACFA (512M words × 72 bits, 4 Ranks)
Specifications
Features
• Density: 4GB
• Organization
512M words × 72 bits, 4 ranks
• Mounting 36 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 4 pieces of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E1206E10 (Ver. 1.0)
Date Published September 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008
1 page  
EBE42AE8ACFA
Serial PD Matrix
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Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 1 0 0 0 08H
128 bytes
256 bytes
DDR2 SDRAM
Number of row address
0 0 0 0 1 1 1 0 0EH
14
Number of column address
0 0 0 0 1 0 1 0 0AH
10
Number of DIMM ranks
0 1 1 0 0 0 1 1 63H
4
Module data width
0 1 0 0 1 0 0 0 48H
72
Module data width continuation
0 0 0 0 0 0 0 0 00H
0
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
SSTL 1.8V
DDR SDRAM cycle time, CL = 5
0 0 1 1 0 0 0 0 30H
3.0ns*1
SDRAM access from clock (tAC)
0 1 0 0 0 1 0 1 45H
0.45ns*1
DIMM configuration type
Refresh rate/type
0 0 0 0 0 1 1 0 06H
1 0 0 0 0 0 1 0 82H
ECC, Address/
Command Parity
7.8µs
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Error checking SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
0
4,8
8
3, 4, 5
4.00mm max.
DIMM type information
0 0 0 0 0 0 0 1 01H
Registered
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at CL = 4 0 0 1 1 1 1 0 1 3DH
Maximum data access time (tAC) from
clock at CL = 4
0
1
0
1
0
0
0
0
50H
Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0 3CH
Normal
Weak Driver
50Ω ODT
Support
3.75ns*1
0.5ns*1
5.0ns*1
0.6ns*1
15ns
Minimum row active to row active
delay (tRRD)
0 0 0 1 1 1 1 0 1EH
Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
7.5ns
15ns
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
Module rank density
0 0 0 0 0 0 0 1 01H
Address and command setup time
before clock (tIS)
0 0 1 0 0 0 0 0 20H
Address and command hold time after
clock (tIH)
0
0
1
0
0
1
1
1
27H
45ns
1GB
0.20ns*1
0.27ns*1
Data Sheet E1206E10 (Ver. 1.0)
5
5 Page 
EBE42AE8ACFA
AC Overshoot/Undershoot Specification (DDR2 SDRAM Component Specification)
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Parameter
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDD
DDR2-667
Maximum undershoot area below VSS
DDR2-667
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDD
DDR2-667
Maximum undershoot area below VSS
DDR2-667
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDDQ
DDR2-667
Maximum undershoot area below VSSQ
DDR2-667
Pins
Command, Address,
CKE, ODT
CK, /CK
DQ, DQS, /DQS,
UDQS, /UDQS,
LDQS, /LDQS,
RDQS, /RDQS,
DM, UDM, LDM
Specification
0.5
0.5
0.8
0.8
0.5
0.5
0.23
0.23
0.5
0.5
0.23
0.23
Unit
V
V
V-ns
V-ns
V
V
V-ns
V-ns
V
V
V-ns
V-ns
Maximum amplitude
Overshoot area
Volts (V) VDD, VDDQ
VSS, VSSQ
Undershoot area
Time (ns)
Overshoot/Undershoot Definition
Data Sheet E1206E10 (Ver. 1.0)
11
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