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PDF EBE41RE4AAHA Data sheet ( Hoja de datos )
| Número de pieza | EBE41RE4AAHA | |
| Descripción | 4GB Registered DDR2 SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
www.DataSheet4U.com
4GB Registered DDR2 SDRAM DIMM
EBE41RE4AAHA (512M words × 72 bits, 2 Ranks)
Specifications
• Density: 4GB
• Organization
⎯ 512M words × 72 bits, 2 ranks
• Mounting 36 pieces of 1G bits DDR2 SDRAM with
sFBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
⎯ PCB height: 30.0mm
⎯ Lead pitch: 1.0mm
⎯ Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 533Mbps/400Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
⎯ Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
⎯ TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E0629E30 (Ver. 3.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2005
1 page  
EBE41RE4AAHA
Serial PD Matrix*1
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Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
2 Memory type
0 0 0 0 1 0 0 0 08H
3 Number of row address
0 0 0 0 1 1 1 0 0EH
4 Number of column address
0 0 0 0 1 0 1 1 0BH
5 Number of DIMM ranks
0 1 1 1 0 0 0 1 71H
6 Module data width
0 1 0 0 1 0 0 0 48H
7 Module data width continuation
0 0 0 0 0 0 0 0 00H
8 Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
DDR SDRAM cycle time, CL = 5
9 -5C
0 0 1 1 1 1 0 1 3DH
-4A
10
SDRAM access from clock (tAC)
-5C
0 1 0 1 0 0 0 0 50H
0 1 0 1 0 0 0 0 50H
-4A 0 1 1 0 0 0 0 0 60H
11 DIMM configuration type
0 0 0 0 0 0 1 0 02H
12 Refresh rate/type
1 0 0 0 0 0 1 0 82H
13 Primary SDRAM width
0 0 0 0 0 1 0 0 04H
14 Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
15 Reserved
0 0 0 0 0 0 0 0 00H
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
18
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
19 Reserved
0 0 0 0 0 0 0 0 00H
20 DIMM type information
0 0 0 0 0 0 0 1 01H
21 SDRAM module attributes
0 0 0 0 0 0 0 0 00H
22
SDRAM device attributes: General
0 0 0 0 0 0 0 1 01H
23
Minimum clock cycle time at CL = 4
0 0 1 1 1 1 0 1 3DH
-5C
-4A 0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC) from
24 clock at CL = 4
0 1 0 1 0 0 0 0 50H
-5C
-4A 0 1 1 0 0 0 0 0 60H
25 Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
26
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
27
Minimum row precharge time (tRP)
0 0 1 1 1 1 0 0 3CH
28
Minimum row active to row active delay
(tRRD)
0
0
0
1
1
1
1
0
1EH
29 Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
Comments
128 bytes
256 bytes
DDR2 SDRAM
14
11
Stack/2 ranks
72
0
SSTL 1.8V
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
ECC
7.8μs
×4
×4
0
4,8
8
3, 4, 5
0
Registered
Normal
Weak Driver
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
5.0ns*1
0.6ns*1
15ns
7.5ns
15ns
Data Sheet E0629E30 (Ver. 3.0)
5
5 Page 
EBE41RE4AAHA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
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Parameter
Operating current
(ACT-PRE)
Symbol Grade
IDD0
-5C
-4A
max
4640
3830
Operating current
(ACT-READ-PRE)
IDD1
-5C
-4A
4950
4050
Precharge power-down
standby current
IDD2P
-5C
-4A
Precharge quiet standby
current
IDD2Q
-5C
-4A
Idle standby current
Active power-down
standby current
Active standby current
IDD2N
-5C
-4A
-5C
IDD3P-F
-4A
-5C
IDD3P-S
-4A
-5C
IDD3N
-4A
1092
912
2100
1740
2460
2100
2460
2100
1560
1200
4460
3740
Operating current
(Burst read operating)
-5C
IDD4R
-4A
6840
5580
Operating current
(Burst write operating)
-5C
IDD4W
-4A
6840
5580
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA
CKE is H, /CS is H;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open;
tCK = tCK (IDD);
mA CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and
address bus inputs are
mA
STABLE;
Data bus inputs are
Slow PDN Exit
MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E0629E30 (Ver. 3.0)
11
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