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EBE41AF4A1QB Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBE41AF4A1QB
Beschreibung 4GB VLP Registered DDR2 SDRAM DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 27 Seiten
EBE41AF4A1QB Datasheet, Funktion
PRELIMINARY DATA SHEET
www.DataSheet4U.com
4GB VLP Registered DDR2 SDRAM DIMM
EBE41AF4A1QB (512M words × 72 bits, 2 Ranks)
Specifications
Density: 4GB
Organization
512M words × 72 bits, 2 ranks
Mounting 18 pieces of 2G bits DDR2 SDRAM with
DDP (FBGA)
DDP: 2 pieces of 1Gb chips sealed in one package
Package: 240-pin very low profile registered
dual in line memory module (VLP RDIMM)
PCB height: 18.3mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
Power supply: VDD = 1.8V ± 0.1V
Data rate: 800Mbps/667Mbps (max.)
Eight internal banks for concurrent operation
(components)
Interface: SSTL_18
Burst lengths (BL): 4, 8
/CAS Latency (CL): 3, 4, 5, 6
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E1246E10 (Ver. 1.0)
Date Published February 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008






EBE41AF4A1QB Datasheet, Funktion
EBE41AF4A1QB
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex vawluwe wC.oDmamtaeSnhtseet4U.com
Maximum data access time (tAC) from
clock at CL = X 2
26 -8G (CL = 4)
0 1 0 1 0 0 0 0 50H
0.5ns*1
-6E (CL = 3)
0 1 1 0 0 0 0 0 60H
0.6ns*1
27
Minimum row precharge time (tRP)
0 0 1 1 1 1 0 0 3CH
15ns
28
Minimum row active to row active delay
(tRRD)
0
0
0
1
1
1
1
0
1EH
7.5ns
29
Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
15ns
30
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
45ns
31 Module rank density
0 0 0 0 0 0 1 0 02H
2GB
Address and command setup time
before clock (tIS)
0 0 0 1 0 1 1 1 17H
0.17ns*1
32 -8G
-6E
0 0 1 0 0 0 0 0 20H
0.20ns*1
Address and command hold time after
clock (tIH)
0 0 1 0 0 1 0 1 25H
0.25ns*1
33 -8G
-6E
0 0 1 0 0 1 1 1 27H
0.27ns*1
34
Data input setup time before clock (tDS)
-8G
0
0
0
0
0
1
0
1
05H
0.05ns*1
-6E
0 0 0 1 0 0 0 0 10H
0.10ns*1
35
Data input hold time after clock (tDH)
-8G
0
0
0
1
0
0
1
0
12H
0.12ns*1
-6E
0 0 0 1 0 1 1 1 17H
0.17ns*1
36 Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
15ns*1
37
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
7.5ns*1
38
Internal read to precharge command
delay (tRTP)
0 0 0 1 1 1 1 0 1EH
7.5ns*1
39
Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
TBD
40 Extension of Byte 41 and 42
41 Active command period (tRC)
0 0 0 0 0 1 1 0 06H
0 0 1 1 1 1 0 0 3CH
60ns*1
42
Auto refresh to active/
Auto refresh command cycle (tRFC)
0 1 1 1 1 1 1 1 7FH
127.5ns*1
43
SDRAM tCK cycle max. (tCK max.)
1 0 0 0 0 0 0 0 80H
8ns*1
Dout to DQS skew
44 -8G
-6E
0 0 0 1 0 1 0 0 14H
0 0 0 1 1 0 0 0 18H
0.20ns*1
0.24ns*1
Data hold skew (tQHS)
45 -8G
-6E
0 0 0 1 1 1 1 0 1EH
0 0 1 0 0 0 1 0 22H
0.30ns*1
0.34ns*1
46 PLL relock time
0 0 0 0 1 1 1 1 0FH
15µs
47 to 61
0 0 0 0 0 0 0 0 00H
62 SPD Revision
0 0 0 1 0 0 1 0 12H
Rev. 1.2
63
Checksum for bytes 0 to 62
-8G
-6E
1 0 1 0 1 1 0 0 ACH
1 1 1 0 0 0 1 0 E2H
64 to 65 Manufacturer’s JEDEC ID code
0 1 1 1 1 1 1 1 7FH
Continuation code
66 Manufacturer’s JEDEC ID code
1 1 1 1 1 1 1 0 FEH
Elpida Memory
67 to 71 Manufacturer’s JEDEC ID code
0 0 0 0 0 0 0 0 00H
Preliminary Data Sheet E1246E10 (Ver. 1.0)
6

6 Page









EBE41AF4A1QB pdf, datenblatt
EBE41AF4A1QB
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Symbol Grade
max
Unit Test condition
Operating current
(ACT-PRE)
IDD0
-8G
-6E
3780
3450
Operating current
(ACT-READ-PRE)
IDD1
-8G
-6E
4220
3840
Precharge power-down
standby current
IDD2P
-8G
-6E
950
890
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby
current
IDD2Q
-8G
-6E
1850
1610
Idle standby current
IDD2N
-8G
-6E
2030
1790
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down
standby current
IDD3P-F
-8G
-6E
IDD3P-S
-8G
-6E
1850
1790
1310
1250
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address
bus inputs are STABLE;
mA Data bus inputs are
FLOATING
Slow PDN Exit
MRS(12) = 1
Active standby current
IDD3N
-8G
-6E
3870
3450
Operating current
(Burst read operating)
IDD4R
-8G
-6E
5300
4650
Operating current
(Burst write operating)
IDD4W
-8G
-6E
5300
4650
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Preliminary Data Sheet E1246E10 (Ver. 1.0)
12

12 Page





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