|
|
Teilenummer | EBE41AE4ACFA |
|
Beschreibung | 4GB Registered DDR2 SDRAM DIMM | |
Hersteller | Elpida Memory | |
Logo | ||
Gesamt 27 Seiten DATA SHEET
www.DataSheet4U.com
4GB Registered DDR2 SDRAM DIMM
EBE41AE4ACFA (512M words × 72 bits, 2 Ranks)
Specifications
• Density: 4GB
• Organization
512M words × 72 bits, 2 ranks
• Mounting 36 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E1078E40 (Ver. 4.0)
Date Published July 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2008
EBE41AE4ACFA
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex vwaluwewC.DoamtamSehnetset4U.com
31 Module rank density
0 0 0 0 0 0 1 0 02H
2GB
Address and command setup time
32 before clock (tIS)
0 0 0 1 0 1 1 1 17H
0.17ns*1
-8E
-6E
0 0 1 0 0 0 0 0 20H
0.20ns*1
Address and command hold time after
33 clock (tIH)
0 0 1 0 0 1 0 1 25H
0.25ns*1
-8E
-6E
0 0 1 0 0 1 1 1 27H
0.27ns*1
34
Data input setup time before clock (tDS)
-8E
0
0
0
0
0
1
0
1
05H
0.05ns*1
-6E
0 0 0 1 0 0 0 0 10H
0.10ns*1
35
Data input hold time after clock (tDH)
-8E
0
0
0
1
0
0
1
0
12H
0.12ns*1
-6E
0 0 0 1 0 1 1 1 17H
0.17ns*1
36 Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
15ns*1
37
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
7.5ns*1
38
Internal read to precharge command
delay (tRTP)
0 0 0 1 1 1 1 0 1EH
7.5ns*1
39
Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
TBD
40
Extension of Byte 41 and 42
-8E
0 0 1 1 0 1 1 0 36H
-6E 0 0 0 0 0 1 1 0 06H
41
Active command period (tRC)
-8E
-6E
0 0 1 1 1 0 0 1 39H
0 0 1 1 1 1 0 0 3CH
57.5ns*1
60ns*1
42
Auto refresh to active/
Auto refresh command cycle (tRFC)
0 1 1 1 1 1 1 1 7FH
127.5ns*1
43
SDRAM tCK cycle max. (tCK max.)
1 0 0 0 0 0 0 0 80H
8ns*1
44
Dout to DQS skew
-8E
-6E
0 0 0 1 0 1 0 0 14H
0 0 0 1 1 0 0 0 18H
0.20ns*1
0.24ns*1
45
Data hold skew (tQHS)
-8E
-6E
0 0 0 1 1 1 1 0 1EH
0 0 1 0 0 0 1 0 22H
0.30ns*1
0.34ns*1
46 PLL relock time
0 0 0 0 1 1 1 1 0FH
15µs
47 to 61
0 0 0 0 0 0 0 0 00H
62 SPD Revision
63
Checksum for bytes 0 to 62
-8E
-6E
0 0 0 1 0 0 1 0 12H
0 0 0 1 0 1 1 1 17H
0 0 1 1 0 0 0 1 31H
Rev. 1.2
64 to 65 Manufacturer’s JEDEC ID code
0 1 1 1 1 1 1 1 7FH
Continuation code
66 Manufacturer’s JEDEC ID code
1 1 1 1 1 1 1 0 FEH
Elpida Memory
67 to 71 Manufacturer’s JEDEC ID code
0 0 0 0 0 0 0 0 00H
72 Manufacturing location
× × × × × × × × ××
(ASCII-8bit code)
73 Module part number
0 1 0 0 0 1 0 1 45H
E
74 Module part number
0 1 0 0 0 0 1 0 42H
B
75 Module part number
0 1 0 0 0 1 0 1 45H
E
Data Sheet E1078E40 (Ver. 4.0)
6
6 Page EBE41AE4ACFA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Symbol Grade
max
Unit Test condition
Operating current
(ACT-PRE)
IDD0
-8E
-6E
3772
3457
Operating current
(ACT-READ-PRE)
IDD1
-8E
-6E
4189
3842
Precharge power-down
standby current
IDD2P
-8E
-6E
940
895
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby
current
IDD2Q
-8E
-6E
1840
1615
Idle standby current
IDD2N
-8E
-6E
2020
1795
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down
standby current
IDD3P-F
-8E
-6E
IDD3P-S
-8E
-6E
1840
1795
1300
1255
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address
bus inputs are STABLE;
mA Data bus inputs are
FLOATING
Slow PDN Exit
MRS(12) = 1
Active standby current
IDD3N
-8E
-6E
3862
3457
Operating current
(Burst read operating)
IDD4R
-8E
-6E
5269
4652
Operating current
(Burst write operating)
IDD4W
-8E
-6E
5269
4652
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E1078E40 (Ver. 4.0)
12
12 Page | ||
Seiten | Gesamt 27 Seiten | |
PDF Download | [ EBE41AE4ACFA Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
EBE41AE4ACFA | 4GB Registered DDR2 SDRAM DIMM | Elpida Memory |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |