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EBE25RC8AAFA Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBE25RC8AAFA
Beschreibung 256MB Registered DDR2 SDRAM DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 22 Seiten
EBE25RC8AAFA Datasheet, Funktion
PRELIMINARY DATA SHEET
www.DataSheet4U.com
256MB Registered DDR2 SDRAM DIMM
EBE25RC8AAFA (32M words × 72 bits, 1 Rank)
Description
Features
The EBE25RC8AAFA is a 32M words × 72 bits, 1 rank
DDR2 SDRAM Module, mounting 9 pieces of DDR2
SDRAM sealed in FBGA package. Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 4bits prefetch-pipelined architecture. Data
strobe (DQS and /DQS) both for read and write are
available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay
Locked Loop (DLL) can be set enable or disable. This
module provides high density mounting without utilizing
surface mount technology. Decoupling capacitors are
mounted beside each FBGA on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free
1.8V power supply
Data rate: 533Mbps/400Mbps (max.)
1.8 V (SSTL_18 compatible) I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, data strobe (DQS and /DQS) is
transmitted /received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Four internal banks for concurrent operation
(Component)
Data mask (DM) for write data
Burst length: 4, 8
/CAS latency (CL): 3, 4, 5
Auto precharge option for each burst access
Auto refresh and self refresh modes
7.8µs average periodic refresh interval
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
1 piece of PLL clock driver, 1 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
Document No. E0470E11 (Ver. 1.1) This product became EOL in April, 2005.
Date Published February 2006 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2006






EBE25RC8AAFA Datasheet, Funktion
EBE25RC8AAFA
www.DataSheet4U.com
Byte No.
27
28
29
30
31
32
33
34
35
36
37
38
39
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Minimum row precharge time (tRP)
0 0 1 1 1 1 0 0 3CH
-5C, -4A
-4C 0 1 0 1 0 0 0 0 50H
Minimum row active to row active
delay (tRRD)
0 0 0 1 1 1 1 0 1EH
Minimum /RAS to /CAS delay (tRCD)
0 0 1 1 1 1 0 0 3CH
-5C, -4A
-4C 0 1 0 1 0 0 0 0 50H
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
Module rank density
0 1 0 0 0 0 0 0 40H
Address and command setup time
before clock (tIS)
-5C
0 0 1 0 0 1 0 1 25H
-4A, -4C
0 0 1 1 0 1 0 1 35H
Address and command hold time after
clock (tIH)
0 0 1 1 1 0 0 0 38H
-5C
-4A, -4C
0 1 0 0 1 0 0 0 48H
Data input setup time before clock
(tDS)
-5C
0 0 0 1 0 0 0 0 10H
-4A, -4C
0 0 0 1 0 1 0 1 15H
Data input hold time after clock (tDH)
0 0 1 0 0 0 1 1 23H
-5C
-4A, -4C
0 0 1 0 1 0 0 0 28H
Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
Internal write to read command delay
(tWTR)
0 0 0 1 1 1 1 0 1EH
-5C
-4A, -4C
0 0 1 0 1 0 0 0 28H
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
Comments
15ns
20ns
7.5ns
15ns
20ns
45ns
256M byte
0.25ns*1
0.35ns*1
0.38ns*1
0.48ns*1
0.10ns*1
0.15ns*1
0.23ns*1
0.28ns*1
15ns*1
7.5ns*1
10ns*1
7.5ns*1
TBD
40 Extension of Byte 41 and 42
0 0 0 0 0 0 0 0 00H
Active command period (tRC)
41
-5C, -4A,
-4C
0 0 1 1 1 1 0 0 3CH
0 1 0 0 0 0 0 1 41H
42
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1
0
0
1
0
1
1
4BH
43 SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H
Dout to DQS skew
44 -5C
0 0 0 1 1 1 1 0 1EH
-4A, -4C
0 0 1 0 0 0 1 1 23H
Data hold skew (tQHS)
45 -5C
0 0 1 0 1 0 0 0 28H
-4A, -4C
0 0 1 0 1 1 0 1 2DH
46 PLL relock time
0 0 0 0 1 1 1 1 0FH
47 to 61
0 0 0 0 0 0 0 0 00H
Undefined
60ns*1
65ns*1
75ns*1
8ns*1
0.30ns*1
0.35ns*1
0.40ns*1
0.45ns*1
15µs
Preliminary Data Sheet E0470E11 (Ver. 1.1)
6

6 Page









EBE25RC8AAFA pdf, datenblatt
EBE25RC8AAFA
www.DataSheet4U.com
Parameter
Symbol Grade
max
Unit Test condition
Auto-refresh current
IDD5
-5C 2730
-4A, -4C 2510
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-refresh current
IDD6
Self Refresh Mode;
CK and /CK at 0V;
80 mA CKE 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating current
(Bank interleaving)
IDD7
-5C 3610
-4A, -4C 3330
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
mA tRCD = 1 × tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN VIL (AC) (max.)
H is defined as VIN VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-533
DDR2-400
Parameter
4-4-4
3-3-3
4-4-4
Unit
CL(IDD)
tRCD(IDD)
tRC(IDD)
tRRD(IDD)-×4/×8
tRRD(IDD)- ×16
tCK(IDD)
tRAS(min.)(IDD)
tRAS(max.)(IDD)
tRP(IDD)
tRFC(IDD)
4
15
60
7.5
10
3.75
45
70000
15
75
3
15
60
7.5
10
5
45
70000
15
75
4
20
65
7.5
10
5
45
70000
20
75
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Data Sheet E0470E11 (Ver. 1.1)
12

12 Page





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