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Número de pieza | EBE21UE8AEFA | |
Descripción | 2GB Unbuffered DDR2 SDRAM DIMM | |
Fabricantes | Elpida Memory | |
Logotipo | ||
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www.DataSheet4U.com
2GB Unbuffered DDR2 SDRAM DIMM
EBE21UE8AEFA (256M words × 64 bits, 2 Ranks)
Specifications
• Density: 2GB
• Organization
256M words × 64 bits, 2 ranks
• Mounting 16 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
(EBE21UE8AEFA-xx-E)
Lead-free (RoHS compliant) and Halogen-free
(EBE21UE8AEFA-xx-F)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E1296E40 (Ver. 4.0)
Date Published January 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008-2009
1 page EBE21UE8AEFA
Serial PD Matrix
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Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0
0
0
0
1
0
0
0
08H
Memory type
0 0 0 0 1 0 0 0 08H
128 bytes
256 bytes
DDR2 SDRAM
Number of row address
0 0 0 0 1 1 1 0 0EH
14
Number of column address
0 0 0 0 1 0 1 0 0AH
10
Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
2
Module data width
0 1 0 0 0 0 0 0 40H
64
Module data width continuation
Voltage interface level of this
assembly
DDR SDRAM cycle time, CL = X
-8G (CL = 6)
-6E (CL = 5)
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 1 0 1 05H
0 0 1 0 0 1 0 1 25H
0 0 1 1 0 0 0 0 30H
0
SSTL 1.8V
2.5ns*1
3.0ns*1
SDRAM access from clock (tAC)
-8G
-6E
0 1 0 0 0 0 0 0 40H
0 1 0 0 0 1 0 1 45H
0.4ns*1
0.45ns*1
DIMM configuration type
0 0 0 0 0 0 0 0 00H
None
Refresh rate/type
1 0 0 0 0 0 1 0 82H
7.8µs
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
None
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
SDRAM device attributes: /CAS
latency
-8G
0 1 1 1 0 0 0 0 70H
-6E 0 0 1 1 1 0 0 0 38H
0
4,8
8
4, 5, 6
3, 4, 5
DIMM Mechanical Characteristics 0 0 0 0 0 0 0 1 01H
4.00mm max.
DIMM type information
0 0 0 0 0 0 1 0 02H
Unbuffered
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
Normal
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at
CL = X − 1
-8G (CL = 5)
0 0 1 1 0 0 0 0 30H
-6E (CL = 4)
0 0 1 1 1 1 0 1 3DH
Maximum data access time (tAC)
from clock at CL = X − 1
-8G (CL = 5)
01
00
01
01
45H
-6E (CL = 4)
0 1 0 1 0 0 0 0 50H
Weak Driver
50Ω ODT Support
3.0ns*1
3.75ns*1
0.45ns*1
0.5ns*1
Minimum clock cycle time at
CL = X − 2
-8G (CL = 4)
-6E (CL = 3)
0 0 1 1 1 1 0 1 3DH
0 1 0 1 0 0 0 0 50H
3.75ns*1
5.0ns*1
Data Sheet E1296E40 (Ver. 4.0)
5
5 Page EBE21UE8AEFA
AC Overshoot/Undershoot Specification (DDR2 SDRAM Component Specification)
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Parameter
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDD
DDR2-800
DDR2-667
Maximum undershoot area below VSS
DDR2-800
DDR2-667
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDD
Maximum undershoot area below VSS
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDDQ
Maximum undershoot area below VSSQ
Pins
Command, Address,
CKE, ODT
CK, /CK
DQ, DQS, /DQS,
UDQS, /UDQS,
LDQS, /LDQS,
RDQS, /RDQS,
DM, UDM, LDM
Specification
0.5
0.5
0.66
0.8
0.66
0.8
0.5
0.5
0.23
0.23
0.5
0.5
0.23
0.23
Unit
V
V
V-ns
V-ns
V-ns
V-ns
V
V
V-ns
V-ns
V
V
V-ns
V-ns
Maximum amplitude
Overshoot area
Volts (V) VDD, VDDQ
VSS, VSSQ
Undershoot area
Time (ns)
Overshoot/Undershoot Definition
Data Sheet E1296E40 (Ver. 4.0)
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet EBE21UE8AEFA.PDF ] |
Número de pieza | Descripción | Fabricantes |
EBE21UE8AEFA | 2GB Unbuffered DDR2 SDRAM DIMM | Elpida Memory |
EBE21UE8AEFB | 2GB Unbuffered DDR2 SDRAM DIMM | Elpida Memory |
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