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PDF EBE21FE8ACWT Data sheet ( Hoja de datos )
| Número de pieza | EBE21FE8ACWT | |
| Descripción | 2GB Fully Buffered DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
www.DataSheet4U.com
2GB Fully Buffered DIMM
EBE21FE8ACWT
Specifications
• Density: 2GB
• Organization
256M words × 72 bits, 2 ranks
• Mounting 18 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Package
240-pin fully buffered, socket type dual in line
memory module (FB-DIMM)
PCB height: 30.35mm
Lead pitch: 1.00mm
Advanced Memory Buffer (AMB): 655-ball FCBGA
Lead-free (RoHS compliant)
• Power supply
DDR2 SDRAM: VDD = 1.8V ± 0.1V
AMB: VCC = 1.5V + 0.075V/ −0.045V
• Data rate: 667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• JEDEC standard Raw Card B Design
• Industry Standard Advanced Memory Buffer (AMB)
• High-speed differential point-to-point link interface at
1.5V (JEDEC spec)
14 north-bound (NB) high speed serial lanes
10 south-bound (SB) high speed serial lanes
• Various features/modes:
MemBIST and IBIST test functions
Transparent mode and direct access mode for
DRAM testing
Interface for a thermal sensor and status indicator
• Channel error detection and reporting
• Automatic DDR2 SDRAM bus and channel
calibration
• SPD (serial presence detect) with 1piece of 256 byte
serial EEPROM
Note: Warranty void if removed DIMM heat
spreader.
Performance
System clock
frequency
167MHz
FB-DIMM
Speed grade
PC2-5300F
Peak channel
throughput
8.0GByte/s
DDR2 SDRAM
FB-DIMM link data rate
4.0Gbps
Speed Grade
DDR data rate
DDR2-667 (5-5-5) 667Mbps
Document No. E1381E10 (Ver. 1.0)
Date Published October 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008
1 page  
EBE21FE8ACWT
Interfaces
www.DataSheet4U.com
Figure Block Diagram AMB Interfaces shows the AMB and all of its interfaces. They consist of two FB-DIMM links,
one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or
an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on an FB-DIMM.
Memory Interface
NB FBD
out Link
SB FBD
in Link
AMB
NB FBD
in Link
SB FBD
out Link
SMB
Block Diagram AMB Interfaces
Interface Topology
The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8
DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven
to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the
next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the
direction on the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives
the data to the next DIMM until the host is reached.
Host
Southbound
Nourthbound
AMB
AMB
AMB
AMB
n/c n/c
Block Diagram FB-DIMM Channel Southbound and Northbound Paths
Data Sheet E1381E10 (Ver. 1.0)
5
5 Page 
EBE21FE8ACWT
AMB Component Timing
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
EI Assertion pass-thru timing
EI deassertion pass-thru timing
Symbol
tEI
propagate
tEID
min. typ.
——
——
EI assertion duration
Resample pass-thru time
tEI 100 —
— 1.075
Resynch pass-thru time
— 2.075
Bit lock Interval
tBitLock
——
Frame lock Interval
tFrameLock
Note: 1. The EI stands for ″Electrical Idle″.
—
—
www.DataSheet4U.com
max.
4
bit lock
—
—
—
119
154
Units
clks
clks
clks
ns
ns
frames
frames
Note
Power Specification Parameter and Test Conditions
Frequency (Mbps)
Parameter
Symbol
Idle Current,
single or last
DIMM
Idd_Idle_0
-6E
667
Power Supply max.
@1.5V
2.60
@1.8V
1.41
Total
6.12
Unit
A
A
W
@1.5V 3.40 A
Idle Current, first
DIMM
Idd_Idle_1
@1.8V
1.41
A
Total
7.37 W
@1.5V 3.90 A
Active Power
Idd_Active_1 @1.8V
2.68
A
Total
10.58
W
@1.5V 3.70 A
Active Power,
data pass through
Idd_Active_2
@1.8V
1.21
A
Total
7.46 W
Training
@1.5V 4.00 A
Idd_Training
(for AMB spec. @1.8V 1.30 A
Not in SPD)
Total
8.11 W
Conditions
L0 state, idle (0 BW)
Primary channel enabled,
Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active.
L0 state, idle (0 BW)
Primary and secondary channels enabled
CKE high. Command and address lines stable.
DRAM clock active.
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and secondary channels enabled.
DRAM clock active, CKE high.
L0 state
50% DRAM BW to downstream DIMM,
67% read, 33% write.
Primary and secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
Primary and secondary channels enabled.
100% toggle on all channel lanes
DRAMs idle. 0 BW.
CKE high, Command and address lines stable.
DRAM clock active.
Note
Data Sheet E1381E10 (Ver. 1.0)
11
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