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EBE21EE8ACFA Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBE21EE8ACFA
Beschreibung 2GB Unbuffered DDR2 SDRAM DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 30 Seiten
EBE21EE8ACFA Datasheet, Funktion
DATA SHEET
www.DataSheet4U.com
2GB Unbuffered DDR2 SDRAM DIMM
EBE21EE8ACFA (256M words × 72 bits, 2 Ranks)
Specifications
Density: 2GB
Organization
256M words × 72 bits, 2 ranks
Mounting 18 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
Power supply: VDD = 1.8V ± 0.1V
Data rate: 800Mbps/667Mbps (max.)
Eight internal banks for concurrent operation
(components)
Interface: SSTL_18
Burst lengths (BL): 4, 8
/CAS Latency (CL): 3, 4, 5, 6
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
Document No. E1060E20 (Ver. 2.0)
Date Published December 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007






EBE21EE8ACFA Datasheet, Funktion
EBE21EE8ACFA
www.DataSheet4U.com
Byte No.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Maximum data access time (tAC)
from clock at CL = X 2
0 1 1 0 0 0 0 0 60H
-8E, -6E (CL = 3)
-8G (CL = 4)
0 1 0 1 0 0 0 0 50H
0.6ns*1
0.5ns*1
Minimum row precharge time (tRP)
-8E
0
0
1
1
0
0
1
0
32H
12.5ns
-8G, -6E
0 0 1 1 1 1 0 0 3CH
15ns
Minimum row active to row active
delay (tRRD)
00
01
11
10
1EH
Minimum /RAS to /CAS delay (tRCD)
-8E
0
0
1
1
0
0
1
0
32H
7.5ns
12.5ns
-8G, -6E
0 0 1 1 1 1 0 0 3CH
15ns
Minimum active to precharge time
(tRAS)
0
0
1
0
1
1
0
1
2DH
45ns
Module rank density
0 0 0 0 0 0 0 1 01H
1G bytes
Address and command setup time
before clock (tIS)
0 0 0 1 0 1 1 1 17H
-8E, -8G
-6E 0 0 1 0 0 0 0 0 20H
0.17ns*1
0.20ns*1
Address and command hold time
after clock (tIH)
-8E, -8G
-6E
0 0 1 0 0 1 0 1 25H
0 0 1 0 0 1 1 1 27H
0.25ns*1
0.27ns*1
Data input setup time before clock
(tDS)
0 0 0 0 0 1 0 1 05H
-8E, -8G
-6E 0 0 0 1 0 0 0 0 10H
0.05ns*1
0.10ns*1
Data input hold time after clock (tDH)
-8E, -8G
0
0
0
1
0
0
1
0
12H
-6E 0 0 0 1 0 1 1 1 17H
0.12ns*1
0.17ns*1
Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
15ns*1
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
Memory analysis probe
characteristics
0 0 0 0 0 0 0 0 00H
Extension of Byte 41 and 42
-8E
0 0 1 1 0 1 1 0 36H
7.5ns*1
7.5ns*1
TBD
-8G, -6E
0 0 0 0 0 1 1 0 06H
Active command period (tRC)
-8E
-8G, -6E
0 0 1 1 1 0 0 1 39H
0 0 1 1 1 1 0 0 3CH
57.5ns*1
60ns*1
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1
1
1
1
1
1
1
7FH
SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H
127.5ns*1
8ns*1
Dout to DQS skew
-8E, -8G
-6E
0 0 0 1 0 1 0 0 14H
0 0 0 1 1 0 0 0 18H
0.20ns*1
0.24ns*1
Data hold skew (tQHS)
-8E, -8G
-6E
0 0 0 1 1 1 1 0 1EH
0 0 1 0 0 0 1 0 22H
0.30ns*1
0.34ns*1
46 PLL relock time
0 0 0 0 0 0 0 0 00H
Undefined
Data Sheet E1060E20 (Ver. 2.0)
6

6 Page









EBE21EE8ACFA pdf, datenblatt
EBE21EE8ACFA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Symbol
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD2P)
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD3N)
Grade
-8E, -8G
-6E
-8E, -8G
-6E
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD2P)
-8E, -8G
-6E
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD3N)
-8E, -8G
-6E
max.
855
810
1575
1440
990
945
1710
1575
Precharge power-down
standby current
IDD2P
180
Precharge quiet standby
current
IDD2Q
-8E, -8G
-6E
630
540
Idle standby current
Active power-down
standby current
IDD2N
-8E, -8G
-6E
720
630
IDD3P-F
-8E, -8G
-6E
630
IDD3P-S
360
Active standby current
IDD3N
-8E, -8G
-6E
1620
1440
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD2P)
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD3N)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD2P)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD3N)
-8E, -8G
-6E
-8E, -8G
-6E
-8E, -8G
-6E
-8E, -8G
-6E
1530
1350
2250
1980
1530
1350
2250
1980
Unit Test condition
mA one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
mA Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address bus
mA
inputs are STABLE;
Slow PDN Exit
Data bus inputs are FLOATING MRS(12) = 1
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E1060E20 (Ver. 2.0)
12

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