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PDF EBE21EE8ABFA Data sheet ( Hoja de datos )
| Número de pieza | EBE21EE8ABFA | |
| Descripción | 2GB Unbuffered DDR2 SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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PRELIMINARY DATA SHEET
www.DataSheet4U.com
2GB Unbuffered DDR2 SDRAM DIMM
EBE21EE8ABFA (256M words × 72 bits, 2 Ranks)
Specifications
• Density: 2GB
• Organization
256M words × 72 bits, 2 ranks
• Mounting 18 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps/533Mbps/400Mbps
(max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E0907E10 (Ver. 1.0)
Date Published June 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006
1 page  
EBE21EE8ABFA
Serial PD Matrix
www.DataSheet4U.com
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0
0
0
0
1
0
0
0
08H
Memory type
0 0 0 0 1 0 0 0 08H
128 bytes
256 bytes
DDR2 SDRAM
Number of row address
0 0 0 0 1 1 1 0 0EH
14
Number of column address
0 0 0 0 1 0 1 0 0AH
10
Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
2
Module data width
0 1 0 0 1 0 0 0 48H
72
Module data width continuation
Voltage interface level of this
assembly
DDR SDRAM cycle time, CL = 5
-8E
-6E
-5C
-4A
SDRAM access from clock (tAC)
-8E
-6E
-5C
-4A
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 1 0 1 05H
0 0 1 0 0 1 0 1 25H
0 0 1 1 0 0 0 0 30H
0 0 1 1 1 1 0 1 3DH
0 1 0 1 0 0 0 0 50H
0 1 0 0 0 0 0 0 40H
0 1 0 0 0 1 0 1 45H
0 1 0 1 0 0 0 0 50H
0 1 1 0 0 0 0 0 60H
0
SSTL 1.8V
2.5ns*1
3.0ns*1
3.75ns*1
5.0ns*1
0.4ns*1
0.45ns*1
0.5ns*1
0.6ns*1
DIMM configuration type
0 0 0 0 0 0 1 0 02H
ECC
Refresh rate/type
1 0 0 0 0 0 1 0 82H
7.8µs
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Error checking SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
DIMM Mechanical Characteristics 0 0 0 0 0 0 0 1 01H
0
4,8
8
3, 4, 5
4.00mm max.
DIMM type information
0 0 0 0 0 0 1 0 02H
Unbuffered
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at CL = 4
-8E, -6E, -5C
0
0
1
1
1
1
0
1
3DH
-4A 0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC)
from clock at CL = 4
-8E, -6E, -5C
01
01
00
00
50H
-4A 0 1 1 0 0 0 0 0 60H
Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
Normal
Weak Driver
50Ω ODT Support
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
5.0ns*1
Maximum data access time (tAC)
from clock at CL = 3
01
10
00
00
60H
0.6ns*1
Preliminary Data Sheet E0907E10 (Ver. 1.0)
5
5 Page 
EBE21EE8ABFA
Electrical Specifications
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• All voltages are referenced to VSS (GND).
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit Notes
Voltage on any pin relative to VSS
VT
–0.5 to +2.3
V1
Supply voltage relative to VSS
VDD
–0.5 to +2.3
V
Short circuit output current
IOS 50
mA 1
Power dissipation
PD 8
W
Operating case temperature
TC 0 to +95
°C 1, 2
Storage temperature
Tstg –55 to +100
°C 1
Notes: 1. DDR2 SDRAM component specification.
2. Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in
frequency to a 32ms period (tREFI = 3.9µs) and higher temperature self-refresh entry via the control of
EMRS (2) bit A7 is required.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC Operating Conditions (TC = 0°C to +85°C) (DDR2 SDRAM Component Specification)
Parameter
Symbol
min.
typ. max.
Unit Notes
Supply voltage
VDD, VDDQ 1.7
1.8 1.9
V4
VSS
0
00
V
VDDSPD
1.7
— 3.6
V
Input reference voltage
VREF
0.49 × VDDQ
0.50 × VDDQ 0.51 × VDDQ
V
1, 2
Termination voltage
VTT
VREF − 0.04
VREF
VREF + 0.04
V
3
DC input logic high
VIH (DC)
VREF + 0.125
VDDQ + 0.3
V
DC input low
AC input logic high
-8E, -6E
-5C, -4A
AC input low
-8E, -6E
-5C, -4A
VIL (DC)
VIH (AC)
VIH (AC)
VIL (AC)
VIL (AC)
−0.3
VREF + 0.200
VREF + 0.250
VREF – 0.125
VREF – 0.200
VREF − 0.250
V
V
V
V
V
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically
the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected
to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ must be equal to VDD
.
Preliminary Data Sheet E0907E10 (Ver. 1.0)
11
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