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EBE20AE4ABFA Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBE20AE4ABFA
Beschreibung 2GB Registered DDR2 SDRAM DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 27 Seiten
EBE20AE4ABFA Datasheet, Funktion
DATA SHEET
www.DataSheet4U.com
2GB Registered DDR2 SDRAM DIMM
EBE20AE4ABFA (256M words × 72 bits, 1 Rank)
Specifications
Density: 2GB
Organization
256M words × 72 bits, 1 rank
Mounting 18 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
Power supply: VDD = 1.8V ± 0.1V
Data rate: 667Mbps (max.)
Eight internal banks for concurrent operation
(components)
Interface: SSTL_18
Burst lengths (BL): 4, 8
/CAS Latency (CL): 3, 4, 5
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E0875E30 (Ver. 3.0)
Date Published December 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006-2007






EBE20AE4ABFA Datasheet, Funktion
EBE20AE4ABFA
Byte No.
35
36
37
38
39
40
41
42
43
44
45
46
47 to 61
62
63
64 to 65
66
67 to 71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Data input hold time after clock
(tDH)
0 0 0 1 0 1 11
Write recovery time (tWR)
0 0 1 1 1 1 00
Internal write to read command
delay (tWTR)
0
0
011
1
10
Internal read to precharge
command delay (tRTP)
0 0 0 1 1 1 10
Memory analysis probe
characteristics
0 0 0 0 0 0 00
Extension of Byte 41 and 42
0 0 0 0 0 1 10
Active command period (tRC)
0 0 1 1 1 1 00
Auto
Auto
refresh
refresh
to active/
command
cycle
(tRFC)
0
1
1
1
1
1
11
SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0
Dout to DQS skew
0 0 0 1 1 0 00
Data hold skew (tQHS)
0 0 1 0 0 0 10
PLL relock time
0 0 0 0 1 1 11
0 0 0 0 0 0 00
SPD Revision
0 0 0 1 0 0 10
Checksum for bytes 0 to 62
0 0 1 1 0 0 00
Manufacturer’s JEDEC ID code 0 1 1 1 1 1 1 1
Manufacturer’s JEDEC ID code 1 1 1 1 1 1 1 0
Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0
Manufacturing location
× × × × × × ××
Module part number
0 1 0 0 0 1 01
Module part number
0 1 0 0 0 0 10
Module part number
0 1 0 0 0 1 01
Module part number
0 0 1 1 0 0 10
Module part number
0 0 1 1 0 0 00
Module part number
0 1 0 0 0 0 01
Module part number
0 1 0 0 0 1 01
Module part number
0 0 1 1 0 1 00
Module part number
0 1 0 0 0 0 01
Module part number
0 1 0 0 0 0 10
Module part number
0 1 0 0 0 1 10
Module part number
0 1 0 0 0 0 01
Module part number
0 0 1 0 1 1 01
Module part number
0 0 1 1 0 1 10
Module part number
0 1 0 0 0 1 01
Module part number
0 0 1 0 1 1 01
Module part number
0 1 0 0 0 1 01
Module part number
0 0 1 0 0 0 00
Revision code
0 0 1 1 0 0 00
Revision code
0 0 1 0 0 0 00
Manufacturing date
× × × × × × ××
Manufacturing date
× × × × × × ××
Hex vwawluwe .CDoamtamSehnetset4U.com
17H 0.17ns*1
3CH
15ns*1
1EH
7.5ns*1
1EH
7.5ns*1
00H
06H
3CH
7FH
80H
18H
22H
0FH
00H
12H
30H
7FH
FEH
00H
××
45H
42H
45H
32H
30H
41H
45H
34H
41H
42H
46H
41H
2DH
36H
45H
2DH
45H
20H
30H
20H
××
××
TBD
60ns*1
127.5ns*1
8ns*1
0.24ns*1
0.34ns*1
15µs
Rev. 1.2
Continuation code
Elpida Memory
(ASCII-8bit code)
E
B
E
2
0
A
E
4
A
B
F
A
6
E
E
(Space)
Initial
(Space)
Year code (BCD)
Week code (BCD)
Data Sheet E0875E30 (Ver. 3.0)
6

6 Page









EBE20AE4ABFA pdf, datenblatt
EBE20AE4ABFA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Operating current
(ACT-PRE)
Symbol Grade max.
IDD0
2390
Operating current
(ACT-READ-PRE)
IDD1
2650
Precharge power-down
standby current
IDD2P
Precharge quiet standby
current
IDD2Q
Idle standby current
IDD2N
Active power-down
standby current
IDD3P-F
IDD3P-S
Active standby current IDD3N
750
1200
1290
1200
930
2030
Operating current
IDD4R
(Burst read operating)
3820
Operating current
IDD4W
(Burst write operating)
3820
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA
tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and
address bus inputs
mA
are STABLE;
Slow PDN Exit
Data bus inputs are MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
mA
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
mA
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E0875E30 (Ver. 3.0)
12

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