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PDF EBE11UD8AHFA Data sheet ( Hoja de datos )
| Número de pieza | EBE11UD8AHFA | |
| Descripción | 1GB Unbuffered DDR2 SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
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PRELIMINARY DATA SHEET
www.DataSheet4U.com
1GB Unbuffered DDR2 SDRAM DIMM
EBE11UD8AHFA (128M words × 64 bits, 2 Ranks)
Specifications
• Density: 1GB
• Organization
⎯ 128M words × 64 bits, 2 ranks
• Mounting 16 pieces of 512M bits DDR2 SDRAM
sealed in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
⎯ PCB height: 30.0mm
⎯ Lead pitch: 1.0mm
⎯ Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps (max.)
• Four internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
⎯ Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
⎯ TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E0941E10 (Ver. 1.0)
Date Published October 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2006
1 page  
EBE11UD8AHFA
Serial PD Matrix
www.DataSheet4U.com
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
10
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 1 0 0 0 08H
128 bytes
256 bytes
DDR2 SDRAM
Number of row address
0 0 0 0 1 1 1 0 0EH
14
Number of column address
0 0 0 0 1 0 1 0 0AH
10
Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
2
Module data width
0 1 0 0 0 0 0 0 40H
64
Module data width continuation
0 0 0 0 0 0 0 0 00H
0
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
DDR SDRAM cycle time, CL = X
-8E (CL = 5)
0 0 1 0 0 1 0 1 25H
-8G (CL = 6)
0 0 1 0 0 1 0 1 25H
SDRAM access from clock (tAC)
0 1 0 0 0 0 0 0 40H
SSTL 1.8V
2.5ns*1
2.5ns*1
0.4ns*1
DIMM configuration type
0 0 0 0 0 0 0 0 00H
None.
Refresh rate/type
1 0 0 0 0 0 1 0 82H
7.8μs
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
None.
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
-8E
0 0 1 1 1 0 0 0 38H
0
4,8
4
3, 4, 5
-8G
0 1 1 1 0 0 0 0 70H
4, 5, 6
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
4.00mm max.
DIMM type information
0 0 0 0 0 0 1 0 02H
Unbuffered
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at CL = X − 1
-8E (CL = 4)
0
0
1
1
1
1
0
1
3DH
-8G (CL = 5)
0 0 1 1 0 0 0 0 30H
Maximum data access time (tAC) from
clock at CL = X − 1
0 1 0 1 0 0 0 0 50H
-8E (CL = 4)
-8G (CL = 5)
0 1 0 0 0 1 0 1 45H
Minimum clock cycle time at CL = X − 2
-8E (CL = 3)
0
1
0
1
0
0
0
0
50H
-8G (CL = 4)
0 0 1 1 1 1 0 1 3DH
Normal
Weak Driver 50Ω
ODT Support
3.75ns*1
3.0ns*1
0.5ns*1
0.45ns*1
5.0ns*1
3.75ns*1
Maximum data access time (tAC) from
clock at CL = X − 2
0 1 1 0 0 0 0 0 60H
-8E (CL = 3)
-8G (CL = 4)
0 1 0 1 0 0 0 0 50H
0.6ns*1
0.5ns*1
Prelinary Data Sheet E0941E10 (Ver. 1.0)
5
5 Page 
EBE11UD8AHFA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Symbol
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD2P)
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD3N)
Grade
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD2P)
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD3N)
Precharge power-down
standby current
IDD2P
Precharge quiet standby
current
IDD2Q
Idle standby current
IDD2N
Active power-down
standby current
IDD3P-F
IDD3P-S
Active standby current
IDD3N
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD2P)
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD3N)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD2P)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD3N)
Auto-refresh current
(Another rank is in IDD2P)
IDD5
Auto-refresh current
(Another rank is in IDD3N)
IDD5
max.
680
1000
760
1080
160
448
560
400
240
800
1160
1480
1200
1520
1640
1960
Unit Test condition
mA one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
mA Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address bus
mA
inputs are STABLE;
Slow PDN Exit
Data bus inputs are FLOATING MRS(12) = 1
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
tCK = tCK (IDD);
mA Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
mA Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Prelinary Data Sheet E0941E10 (Ver. 1.0)
11
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