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PDF EBE11UD8AGUA Data sheet ( Hoja de datos )
| Número de pieza | EBE11UD8AGUA | |
| Descripción | 1GB DDR2 SDRAM SO-DIMM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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DATA SHEET
www.DataSheet4U.com
1GB DDR2 SDRAM SO-DIMM
EBE11UD8AGUA (128M words × 64 bits, 2 Ranks)
Specifications
• Density: 1GB
• Organization
⎯ 128M words × 64 bits, 2 ranks
• Mounting 16 pieces of 512M bits DDR2 SDRAM
sealed in FBGA
• Package: 200-pin socket type small outline dual in
line memory module (SO-DIMM)
⎯ PCB height: 30.0mm
⎯ Lead pitch: 0.6mm
⎯ Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 667Mbps/533Mbps (max.)
• Four internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
⎯ Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
⎯ TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E0918E20 (Ver. 2.0)
Date Published May 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2006-2007
1 page  
EBE11UD8AGUA
Serial PD Matrix
www.DataSheet4U.com
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Memory type
Hex
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 value
1 0 0 0 0 0 0 0 80H
0 0 0 0 1 0 0 0 08H
0 0 0 0 1 0 0 0 08H
Number of row address
0 0 0 0 1 1 1 0 0EH
Number of column address
0 0 0 0 1 0 1 0 0AH
Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
Module data width
0 1 0 0 0 0 0 0 40H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
DDR SDRAM cycle time, CL = 5
-6E
0 0 1 1 0 0 0 0 30H
-5C 0 0 1 1 1 1 0 1 3DH
SDRAM access from clock (tAC)
-6E
0 1 0 0 0 1 0 1 45H
-5C 0 1 0 1 0 0 0 0 50H
DIMM configuration type
0 0 0 0 0 0 0 0 00H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
DIMM type information
0 0 0 0 0 1 0 0 04H
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
22 SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
23 Minimum clock cycle time at CL = 4 0 0 1 1 1 1 0 1 3DH
24
Maximum data access time (tAC) from
clock at CL = 4
0
1
0
1
0
0
0
0
50H
25 Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
26
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
27 Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0 3CH
28
Minimum row active to row active
delay (tRRD)
0 0 0 1 1 1 1 0 1EH
29 Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
30
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
31 Module rank density
1 0 0 0 0 0 0 0 80H
Comments
128 bytes
256 bytes
DDR2 SDRAM
14
10
2
64
0
SSTL 1.8V
3.0ns*1
3.75ns*1
0.45ns*1
0.5ns*1
None.
7.8μs
×8
None.
0
4,8
4
3, 4, 5
3.80mm max.
SO-DIMM
Normal
Weak Driver
50Ω ODT Support
3.75ns*1
0.5ns*1
5.0ns*1
0.6ns*1
15ns
7.5ns
15ns
45ns
512M bytes
Data Sheet E0918E20 (Ver. 2.0)
5
5 Page 
EBE11UD8AGUA
www.DataSheet4U.com
Parameter
Symbol Grade
max.
Unit Test condition
Auto-refresh current
(Another rank is in IDD2P)
IDD5
Auto-refresh current
(Another rank is in IDD3N)
IDD5
-6E
-5C
-6E
-5C
2240
2080
2720
2520
tCK = tCK (IDD);
mA Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
mA Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-refresh current
IDD6
Self Refresh Mode;
CK and /CK at 0V;
96 mA CKE ≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating current
(Bank interleaving)
IDD7
(Another rank is in IDD2P)
Operating current
(Bank interleaving)
IDD7
(Another rank is in IDD3N)
-6E
-5C
2640
3120
3080
all bank interleaving reads, IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1 × tCK (IDD);
CKE is H, CS is H between valid commands;
mA Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤ VIL (AC) (max.)
H is defined as VIN ≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667
DDR2-533
Parameter
5-5-5
4-4-4
CL(IDD)
5
4
tRCD(IDD)
15
15
tRC(IDD)
60
60
tRRD(IDD)
7.5
7.5
tCK(IDD)
3
3.75
tRAS(min.)(IDD)
45
45
tRAS(max.)(IDD)
70000
70000
tRP(IDD)
15
15
tRFC(IDD)
105
105
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet E0918E20 (Ver. 2.0)
11
11 Page | ||
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