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EBE11UD8AEFA-6 Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBE11UD8AEFA-6
Beschreibung 1GB Unbuffered DDR2 SDRAM DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 22 Seiten
EBE11UD8AEFA-6 Datasheet, Funktion
DATA SHEET
www.DataSheet4U.com
1GB Unbuffered DDR2 SDRAM DIMM
EBE11UD8AEFA-6 (128M words × 64 bits, 2 Ranks)
Description
The EBE11UD8AEFA is 128M words × 64 bits, 2 ranks
DDR2 SDRAM unbuffered module, mounting 16 pieces
of 512M bits DDR2 SDRAM sealed in FBGA (µBGA)
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 4 bits prefetch-
pipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each FBGA (µBGA) on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free
Power supply: VDD = 1.8V± 0.1V
Data rate: 667Mbps (max.)
SSTL_18 compatible I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
(components)
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
Document No. E0721E10 (Ver. 1.0)
Date Published May 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005






EBE11UD8AEFA-6 Datasheet, Funktion
EBE11UD8AEFA-6
www.DataSheet4U.com
Byte No.
36
37
38
39
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
15ns*1
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
7.5ns*1
7.5ns*1
Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
TBD
40 Extension of Byte 41 and 42
0 0 0 0 0 0 0 0 00H
41 Active command period (tRC)
0 0 1 1 1 1 0 0 3CH
42
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1
1
0
1
0
0
1
69H
43 SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H
44 Dout to DQS skew
0 0 0 1 1 0 0 0 18H
45 Data hold skew (tQHS)
0 0 1 0 0 0 1 0 22H
46 PLL relock time
0 0 0 0 0 0 0 0 00H
47 to 61
0 0 0 0 0 0 0 0 00H
Undefined
60ns*1
105ns*1
8ns*1
0.24ns*1
0.34ns*1
Undefined
62 SPD Revision
0 0 0 1 0 0 1 0 12H
Rev. 1.2
63 Checksum for bytes 0 to 62
0 1 1 1 0 1 0 0 74H
64 to 65 Manufacturer’s JEDEC ID code
0 1 1 1 1 1 1 1 7FH
Continuation code
66
67 to 71
72
73
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturing location
Module part number
1 1 1 1 1 1 1 0 FEH
0 0 0 0 0 0 0 0 00H
× × × × × × × × ××
0 1 0 0 0 1 0 1 45H
Elpida Memory
(ASCII-8bit code)
E
74 Module part number
0 1 0 0 0 0 1 0 42H
B
75 Module part number
0 1 0 0 0 1 0 1 45H
E
76 Module part number
77 Module part number
78 Module part number
0 0 1 1 0 0 0 1 31H
0 0 1 1 0 0 0 1 31H
0 1 0 1 0 1 0 1 55H
1
1
U
79 Module part number
0 1 0 0 0 1 0 0 44H
D
80 Module part number
0 0 1 1 1 0 0 0 38H
8
81 Module part number
0 1 0 0 0 0 0 1 41H
A
82 Module part number
83 Module part number
84 Module part number
0 1 0 0 0 1 0 1 45H
0 1 0 0 0 1 1 0 46H
0 1 0 0 0 0 0 1 41H
E
F
A
85 Module part number
0 0 1 0 1 1 0 1 2DH
86 Module part number
0 0 1 1 0 1 1 0 36H
6
87 Module part number
0 1 0 0 0 1 0 1 45H
E
88 Module part number
89 Module part number
90 Module part number
0 0 1 0 1 1 0 1 2DH
0 1 0 0 0 1 0 1 45H
0 0 1 0 0 0 0 0 20H
E
(Space)
91 Revision code
0 0 1 1 0 0 0 0 30H
Initial
92
93
94
95 to 98
Revision code
Manufacturing date
Manufacturing date
Module serial number
0 0 1 0 0 0 0 0 20H
× × × × × × × × ××
× × × × × × × × ××
(Space)
Year code (BCD)
Week code (BCD)
Data Sheet E0721E10 (Ver. 1.0)
6

6 Page









EBE11UD8AEFA-6 pdf, datenblatt
EBE11UD8AEFA-6
www.DataSheet4U.com
Parameter
Symbol Grade
max.
Unit Test condition
Self-refresh current
IDD6
Self Refresh Mode;
CK and /CK at 0V;
96 mA CKE 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating current
(Bank interleaving)
IDD7
(Another rank is in IDD2P)
Operating current
(Bank interleaving)
IDD7
(Another rank is in IDD3N)
2640
3120
all bank interleaving reads, IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1 × tCK (IDD);
CKE is H, CS is H between valid commands;
mA Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN VIL (AC) (max.)
H is defined as VIN VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667
Parameter
CL (IDD)
5-5-5
5
tRCD (IDD)
15
tRC (IDD)
60
tRRD (IDD)
7.5
tCK (IDD)
3
tRAS (min.)(IDD)
45
tRAS (max.)(IDD)
70000
tRP (IDD)
15
tRFC (IDD)
105
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet E0721E10 (Ver. 1.0)
12

12 Page





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