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Teilenummer | EBE10UE8AEWA |
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Beschreibung | 1GB Unbuffered DDR2 SDRAM DIMM | |
Hersteller | Elpida Memory | |
Logo | ||
Gesamt 30 Seiten PRELIMINARY DATA SHEET
www.DataSheet4U.com
1GB Unbuffered DDR2 SDRAM DIMM
EBE10UE8AEWA (128M words × 64 bits, 1 Rank)
Specifications
• Density: 1GB
• Organization
128M words × 64 bits, 1 rank
• Mounting 8 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E1293E10 (Ver. 1.0)
Date Published March 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008
EBE10UE8AEWA
www.DataSheet4U.com
Byte No.
26
Function described
Maximum data access time (tAC)
from clock at CL = X − 2
-8G (CL = 4)
-6E (CL = 3)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0 1 0 1 0 0 0 0 50H
0.5ns*1
0 1 1 0 0 0 0 0 60H
0.6ns*1
27
Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0 3CH
15ns
28
Minimum row active to row active
delay (tRRD)
00
01
11
10
1EH
7.5ns
29
Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
15ns
30
Minimum active to precharge time
(tRAS)
0
0
1
0
1
1
0
1
2DH
45ns
31 Module rank density
0 0 0 0 0 0 0 1 01H
1G bytes
Address and command setup time
32 before clock (tIS)
0 0 0 1 0 1 1 1 17H
0.17ns*1
-8G
-6E
0 0 1 0 0 0 0 0 20H
0.20ns*1
Address and command hold time
33 after clock (tIH)
0 0 1 0 0 1 0 1 25H
0.25ns*1
-8G
-6E
0 0 1 0 0 1 1 1 27H
0.27ns*1
Data input setup time before clock
34 (tDS)
0 0 0 0 0 1 0 1 05H
0.05ns*1
-8G
-6E
0 0 0 1 0 0 0 0 10H
0.10ns*1
35
Data input hold time after clock (tDH)
-8G
0
0
0
1
0
0
1
0
12H
0.12ns*1
-6E
0 0 0 1 0 1 1 1 17H
0.17ns*1
36 Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
15ns*1
37
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
7.5ns*1
38
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
7.5ns*1
39
Memory analysis probe
characteristics
0 0 0 0 0 0 0 0 00H
TBD
40 Extension of Byte 41 and 42
0 0 0 0 0 1 1 0 06H
41
Active command period (tRC)
0 0 1 1 1 1 0 0 3CH
60ns*1
42
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1
1
1
1
1
1
1
7FH
127.5ns*1
43
SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H
8ns*1
44
Dout to DQS skew
-8G
-6E
0 0 0 1 0 1 0 0 14H
0 0 0 1 1 0 0 0 18H
0.20ns*1
0.24ns*1
45
Data hold skew (tQHS)
-8G
-6E
0 0 0 1 1 1 1 0 1EH
0 0 1 0 0 0 1 0 22H
0.30ns*1
0.34ns*1
46 PLL relock time
0 0 0 0 0 0 0 0 00H
Undefined
Preliminaly Data Sheet E1293E10 (Ver. 1.0)
6
6 Page EBE10UE8AEWA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Operating current
(ACT-PRE)
Symbol Grade
IDD0
-8G
-6E
Operating current
(ACT-READ-PRE)
IDD1
-8G
-6E
Precharge power-down
standby current
IDD2P
Precharge quiet standby
current
IDD2Q
-8G
-6E
Idle standby current
IDD2N
-8G
-6E
Active power-down
standby current
IDD3P-F
IDD3P-S
Active standby current
IDD3N
-8G
-6E
Operating current
(Burst read operating)
IDD4R
-8G
-6E
Operating current
(Burst write operating)
IDD4W
-8G
-6E
max.
680
640
800
760
80
280
240
320
280
280
160
720
640
1280
1120
1280
1120
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address bus
mA
inputs are STABLE;
Slow PDN Exit
Data bus inputs are FLOATING MRS(12) = 1
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
mA
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
mA
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Preliminaly Data Sheet E1293E10 (Ver. 1.0)
12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ EBE10UE8AEWA Schematic.PDF ] |
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