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EBE10AE8ACFA Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBE10AE8ACFA
Beschreibung 1GB Registered DDR2 SDRAM DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 27 Seiten
EBE10AE8ACFA Datasheet, Funktion
DATA SHEET
www.DataSheet4U.com
1GB Registered DDR2 SDRAM DIMM
EBE10AE8ACFA (128M words × 72 bits, 1 Rank)
Specifications
Density: 1GB
Organization
128M words × 72 bits, 1 rank
Mounting 9 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
Package: 240-pin socket type dual in line memory
module (DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
Power supply: VDD = 1.8V ± 0.1V
Data rate: 800Mbps/667Mbps (max.)
Eight internal banks for concurrent operation
(components)
Interface: SSTL_18
Burst lengths (BL): 4, 8
/CAS Latency (CL): 3, 4, 5
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
1 piece of PLL clock driver, 1 piece of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E1074E30 (Ver. 3.0)
Date Published July 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2007-2008






EBE10AE8ACFA Datasheet, Funktion
EBE10AE8ACFA
www.DataSheet4U.com
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
31 Module rank density
0 0 0 0 0 0 0 1 01H
Address and command setup time
32 before clock (tIS)
0 0 0 1 0 1 1 1 17H
-8E
-6E 0 0 1 0 0 0 0 0 20H
Address and command hold time after
33 clock (tIH)
0 0 1 0 0 1 0 1 25H
-8E
-6E 0 0 1 0 0 1 1 1 27H
Data input setup time before clock
34 (tDS)
0 0 0 0 0 1 0 1 05H
-8E
-6E 0 0 0 1 0 0 0 0 10H
35
Data input hold time after clock (tDH)
-8E
0
0
0
1
0
0
1
0
12H
-6E 0 0 0 1 0 1 1 1 17H
36 Write recovery time (tWR)
0 0 1 1 1 1 0 0 3CH
37
Internal write to read command delay
(tWTR)
0
0
0
1
1
1
1
0
1EH
38
Internal read to precharge command
delay (tRTP)
0
0
0
1
1
1
1
0
1EH
39 Memory analysis probe characteristics 0 0 0 0 0 0 0 0 00H
40
Extension of Byte 41 and 42
-8E
0 0 1 1 0 1 1 0 36H
-6E 0 0 0 0 0 1 1 0 06H
41
Active command period (tRC)
-8E
0 0 1 1 1 0 0 1 39H
-6E 0 0 1 1 1 1 0 0 3CH
42
Auto refresh to active/
Auto refresh command cycle (tRFC)
0
1
1
1
1
1
1
1
7FH
43 SDRAM tCK cycle max. (tCK max.) 1 0 0 0 0 0 0 0 80H
44
Dout to DQS skew
-8E
0 0 0 1 0 1 0 0 14H
-6E 0 0 0 1 1 0 0 0 18H
45
Data hold skew (tQHS)
-8E
0 0 0 1 1 1 1 0 1EH
-6E 0 0 1 0 0 0 1 0 22H
46 PLL relock time
0 0 0 0 1 1 1 1 0FH
47 to 61
0 0 0 0 0 0 0 0 00H
62 SPD Revision
63
Checksum for bytes 0 to 62
-8E
-6E
0 0 0 1 0 0 1 0 12H
0 0 0 1 1 1 0 0 1CH
0 0 1 1 0 1 1 0 36H
64 to 65 Manufacturer’s JEDEC ID code
0 1 1 1 1 1 1 1 7FH
66
Manufacturer’s JEDEC ID code
1 1 1 1 1 1 1 0 FEH
1GB
0.17ns*1
0.20ns*1
0.25ns*1
0.27ns*1
0.05ns*1
0.10ns*1
0.12ns*1
0.17ns*1
15ns*1
7.5ns*1
7.5ns*1
TBD
57.5ns*1
60ns*1
127.5ns*1
8ns*1
0.20ns*1
0.24ns*1
0.30ns*1
0.34ns*1
15µs
Rev. 1.2
Continuation
code
Elpida Memory
67 to 71 Manufacturer’s JEDEC ID code
72 Manufacturing location
73 Module part number
0 0 0 0 0 0 0 0 00H
× × × × × × × × ××
0 1 0 0 0 1 0 1 45H
(ASCII-8bit
code)
E
74 Module part number
0 1 0 0 0 0 1 0 42H
B
Data Sheet E1074E30 (Ver. 3.0)
6

6 Page









EBE10AE8ACFA pdf, datenblatt
EBE10AE8ACFA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Operating current
(ACT-PRE)
Symbol Grade
IDD0
-8E
-6E
max.
1357
1277
Operating current
(ACT-READ-PRE)
IDD1
-8E
-6E
1573
1475
Precharge power-down
standby current
IDD2P
-8E
-6E
Precharge quiet standby
current
IDD2Q
-8E
-6E
Idle standby current
IDD2N
-8E
-6E
Active power-down
standby current
IDD3P-F
-8E
-6E
IDD3P-S
-8E
-6E
659
623
884
803
929
848
884
848
749
713
Active standby current
IDD3N
-8E
-6E
1402
1277
Operating current
(Burst read operating)
IDD4R
-8E
-6E
2113
1880
Operating current
(Burst write operating)
IDD4W
-8E
-6E
2113
1880
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);CKE is H, /CS is H;
mA Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and
address bus inputs are
STABLE;
mA Data bus inputs are
Slow PDN Exit
MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E1074E30 (Ver. 3.0)
12

12 Page





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