PDF WC32P020-XXM Data sheet ( Hoja de datos )

Número de pieza	WC32P020-XXM
Descripción	16 32-Bit General-Purpose Data and Address Registers
Fabricantes	White Electronic Designs Corporation
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White Electronic Designs WC32P020-XXM www.DataSheet4U.com 68020 FEATURES Selection of Processor Speeds: 16.67, 20, 25 MHz Military Temperature Range: -55°C to +125°C Packaging •114 pin Ceramic PGA (P2) •132 lead Ceramic Quad Flatpack, CQFP (Q2) Object-code compatible with earlier 68000 Microprocessors Addressing mode extensions for enhanced support of high-level languages Bit Field Data Type Accelerates Bit-Oriented Applications–i.e., Video Graphics Fast On-Chip Instruction Cache Speeds Instructions and Improves Bus Bandwidth Coprocessor Interface to Companion 32-Bit Peripherals–the 68881 and 68882 Floating-Point Coprocessors and the 68851 Paged Memory Management Unit Pipelined Architecture with High Degree of Internal Parallelism allowing Multiple Instructions to be executed concurrently High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32-Bits Dynamic Bus Sizing Efﬁciently Supports 8-/16-/32- Bit Memories and Peripherals Full Support of Virtual Memory and Virtual Machine 16 32-Bit General-Purpose Data and Address Registers Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers 18 Addressing Modes and 7 Data Types 4 GigaByte Direct Addressing Range DESCRIPTION The WC32P020 is a 32-bit implementation of the 68000 Family of microprocessors. Using HCMOS technology, the WC32P020 is implemented with 32-bit registers and data paths, 32-bit addresses, a powerful instruction set, and ﬂexible addressing modes. FIGURE 1 – BLOCK DIAGRAM MICRO MACHINE MICROROM NANOROM CONTROL SECTION SEQUENCER INSTRUCTION DECODE INSTRUCTION PIPE TAG CACHE EXECUTION UNIT INSTRUCTION OPERAND ADDRESS ADDRESS SECTION SECTION DATA SECTION INSTRUCTION CACHE ADDRESS PADS BUS CONTROLLER DATA PADS BUS CONTROLLER White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. December 2002 Rev. 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs WC32P020-XXM www.DataSheet4U.com Signal Name Function Codes Address Bus Data Bus Size External Cycle Start Operand Cycle Start Read,Write Read-Modify-Write Cycle Address Strobe Data Strobe Data Buffer Enable Data Transfer and Size Acknowledge Interrupt Priority Level Interrupt Pending Autovector Bus Request Bus Grant Bus Grant Acknowledge Reset Halt Bus Error Cache Disable Clock Power Supply Ground Mnemonic FC2-FC0 A0-A31 D0-D31 SIZ0/SIZ1 ECS# OCS# R/W# RMC# AS# DS# DBEN# DSACK0#/DSACK1# IPL0#-IPL2# IPEND# AVEC# BR# BG# BGACK# RESET# HALT# BERR# CDIS# CLK Vcc GND SIGNAL INDEX Function 3-bit function code used to identify the address space of each bus cycle. 32-bit address bus. 32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus cycle. Indicates the number of bytes remaining to be transferred for this cycle. These signals, together with A1 and A0, deﬁne the active sections of the data bus. Provides an indication that a bus cycle is beginning. Identical operation to that of ECS except that OCS is asserted only during the ﬁrst bus cycle of an operand transfer. Deﬁnes the bus transfer as a processor read or write. Provides an indicator that the current bus cycle is part of an indivisible read-modify-write operation. Indicates that a valid address is on the bus. Indicates that valid data is to be placed on the data bus by an external device or has been placed on the data bus by the WC32P020-XXM. Provides an enable signal for external data buffers. Bus response signals that indicate the requested data transfer operation has completed. In addition, these two lines indicate the size of the external bus port on a cycle-by-cycle basis and are used for asynchronous transfers. Provides an encoded interrupt level to the processor. Indicates that an interrupt is pending. Requests an autovector during an interrupt acknowledge cycle. Indicates that an external device requires bus mastership. Indicates that an external device may assume bus mastership. Indicates that an external device has assumed bus mastership. System reset. Indicates that the processor should suspend bus activity. Indicates that an erroneous bus operation is being attempted. Dynamically disables the on-chip cache to assist emulator support Clock input to the processor. Power supply. Ground connection. White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. December 2002 Rev. 2 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs WC32P020-XXM www.DataSheet4U.com FIGURE 7 – WRITE CYCLE TIMING DIAGRAM CLK A31-A0 S0 S1 S2 S3 S4 S5 6 7 FC2-FC0 10 SIZE 12A 8 ECS# 6A OCS# 10A 11 AS# 9 DS# R/W# 20 22 14 14A 12 9 46 13 15 17 DSACK0# 31A 28 DSACK1# 55 23 53 D31-D0 44 26 25 DBEN# BERR# 42 45 48 43 HALT# 27A NOTE: Timing measurements are referenced to and from a low 0.8V and a high voltage of 2.0V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8V and 2.0V. White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. December 2002 Rev. 2 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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