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A1448 Schematic ( PDF Datasheet ) - Allegro MicroSystems

Teilenummer A1448
Beschreibung Low-Voltage Full-Bridge Brushless DC Motor Driver
Hersteller Allegro MicroSystems
Logo Allegro MicroSystems Logo 




Gesamt 7 Seiten
A1448 Datasheet, Funktion
A1448
www.DataSheet4U.com
Low-Voltage, Full-Bridge Brushless DC Motor Driver with
Integrated Hall Sensor IC, PWM Speed Control, Soft-Switching,
and Reverse Battery and Short Circuit Protection
Features and Benefits
Low-voltage operation, 1.8 to 4.2 V
Multifunction CONTROL pin input:
Direct input PWM for speed control
Active braking for fast stop cycle
Sleep function to reduce average power consumption
Reverse voltage protection on VDD and CONTROL pins
Output thermal shutdown protection for robust performance
Soft switching algorithm to reduce audible switching noise
and EMI
Hall chopper stabilization technique for precise signal
response over operating range
Antistall feature guarantees continuous rotation and
prevents overheating
Single-chip solution for high reliability
Miniature MLP/DFN package with industry-leading
0.40 mm maximum overall thickness
Package:
6-contact MLP/DFN
1.5 mm × 2 mm
0.40 mm maximum overall height
(EW package)
Approximate size
Description
The A1448 is a full-bridge motor driver designed to drive
low-voltage, brushless DC motors. The device is designed
to allow the user to control several functions with a single
input control pin. The pin allows for direct input PWM for
speed control, is used to initiate the active braking func-
tion to reduce motor stop time, and acts as an enable pin to
engage micro-power sleep mode to reduce average power
consumption when not in use. The A1448 is designed for
use in vibration motor applications in portable devices that
require fast stop-start cycles, such as haptic applications and
vibration ring tones.
Commutation of the motor is achieved by use of a single
Hall element to detect the rotational position of an alternat-
ing-pole ring magnet. A high density CMOS semiconductor
process allows the integration of all the necessary electron-
ics. This includes the Hall element, the motor control cir-
cuitry, and the output full bridge. Low-voltage design tech-
niques have been employed to achieve full device function-
ality down to 1.8 V VDD. This fully integrated single chip
solution provides enhanced reliability (including reverse
battery protection and output short circuit protection) and
eliminates the need for any external support components.
The A1448 employs a soft-switching algorithm to reduce
audible switching noise and EMI interference. The micro-
power sleep mode can be initiated on the CONTROL pin,
and reduces current consumption for battery management in
Continued on the next page…
Functional Block Diagram
VDD
Reverse Battery
ESD
CONTROL
To All Subcircuits
Active Braking
Sleep Mode
PWM Control
Drive
Logic
Full Bridge
Q1
Amp
Stall Detection
Thermal Shutdown
Protection
Q3
Q2
VOUT1
ESD
VOUT2
Q4
1448-DS, Rev. 3
GND






A1448 Datasheet, Funktion
A1448
Low-Voltage, Full-Bridge Brushless DC Motor Driver with
Integrated Hall Sensor IC, PWM Speed Conwtrwowl.,DSatoafSht-eSetw4Ui.tccohming,
and Reverse Battery and Short Circuit Protection
Power Derating
The device must be operated below the maximum junction tem-
perature of the device, TJ (max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems website.)
The package thermal resistance, RθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the effective thermal conductivity, K, of
the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RθJC, is relatively
small component of RθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at various PD levels.
PD = VIN × IIN
ΔT = PD × RθJA
(1)
(2)
TJ = TA + ΔT
(3)
For a load of 30 Ω, and given common conditions such as:
TA= 25°C, VDD = 3 V, IDD = 83 mA, VLOAD = 2.43 V,
ILOAD = 81 mA, and RθJA = 125 °C/W, (see figure 5)
then:
PD = VDD × IDD – VLOAD × ILOAD
= 3 V × 83 mA – 2.43 V × 81 mA
= 52.17 mW
ΔT = PD × RθJA
= 52.17 mW × 125 °C/W
= 7°C
TJ = TA + ΔT
= 25°C + 7°C
= 32°C
A worst-case estimate, PD(max), represents the maximum allow-
able power level, without exceeding TJ(max), at a selected RθJA
and TA.
VBATT
CBYP
VDD
VOUT2
A1448
CONTROL
VOUT1
NC GND
M
Figure 5. A1448 typical application
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6

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