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ADUC7122 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADUC7122
Beschreibung Precision Analog Microcontroller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADUC7122 Datasheet, Funktion
Data Sheet
Precision Analog Microcontroller, 12-Bit
Analog I/O, ARM7TDMI MCU
ADuC7122
FEATURES
Analog I/O
13-external channel, 12-bit, 1 MSPS ADC
2 differential channels with programmable gain
PGA (1 to 5) input range
IOVDD power monitor channel
On-chip temperature monitor
11 general-purpose inputs
Fully differential and single-ended modes
0 V to VREF analog input range
12 × 12-bit voltage output DACs
On-chip voltage reference: 1.2 V/2.5 V
Buffered output reference sources for use with external
circuits
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 41.78 MHz
41.78 MHz PLL with programmable divider
Memory
126 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
On-chip peripherals
UART, 2× I2C and SPI serial I/Os
32-pin GPIO port
4 general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
Power
Specified for 3 V operation
Active mode: 11 mA at 5 MHz, 40 mA at 41.78 MHz
Packages and temperature range
7 mm × 7 mm 108-ball BGA
Fully specified for −10°C to +95°C operation
Tools
Low cost QuickStart development system
Full third-party support
APPLICATIONS
Optical networking, industrial control, and automation
systems
Smart sensors and precision instrumentation
FUNCTIONAL BLOCK DIAGRAM
AVDD 3.3V AGND DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC8
PADC0
PGA
PADC1
PGA
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
TEMPERATURE IOVDD MON
SENSOR
INTERNAL
REFERENCE
BUF
VREF_1.2 VREF_2.5
DAC BUF
DAC9
DAC BUF
DAC10
1MSPS
12-BIT
SAR ADC
ADuC7122
DAC BUF
PLA
OSC
PLL
POR
PWM
WAKE-UP
TIMER
WD
TIMER
VIC
3× GP
TIMERS
126k
FLASH
(63k ×
16-BIT)
8k SRAM
(2k × 32-BIT)
ARM7
TDMI
LDO
UART
JTAG
GPIO
CONTROL
SPI
12C × 2
P0.0 TO P0.7
P1.0 TO P1.7
Figure 1.
P2.0 TO P2.7
P3.0 TO P3.7
DAC11
IOVDD
IOGND
XTALI
XTALO
RST
TDO
TDI
TCK
TMS
TRST
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADUC7122 Datasheet, Funktion
ADuC7122
Data Sheet
Parameter
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Accuracy7
Reference Temperature Coefficient4
Power Supply Rejection Ratio
Output Impedance
Internal VREF Power-On Time
EXTERNAL REFERENCE INPUT
Input Voltage Range
BUF_VREF1, BUF_VREF2 OUTPUTS
Accuracy
Reference Temperature Coefficient
Load Current
DAC CHANNEL SPECIFICATIONS
DC Accuracy8
Resolution
Relative Accuracy
Differential Nonlinearity
Calculated Offset Error
Actual Offset Error
Gain Error9
Gain Error Mismatch
Settling Time
PSRR4
DC
1 kHz
10 kHz
100 kHz
OFFSET DRIFT4
GAIN ERROR DRIFT4
SHORT-CIRCUIT CURRENT
ANALOG OUTPUTS
Output Range
Min
1.2
−59
−57
−47
−19
0.1
DAC AC CHARACTERISTICS
Slew Rate
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
Typ
2.5
10
61
10
1
±30
40
12
±2
±0.2
±2
9
±0.15
0.1
10
−61
20
2.49
10
±20
TEMPERATURE SENSOR10
Voltage Output at 25°C
Voltage TC
Accuracy
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection
Power Supply Trip Point Accuracy
POWER-ON RESET
WATCHDOG TIMER (WDT)
Timeout Period
0
707
−1.25
±3
2.79
3.07
±2.5
2.36
Max Unit
V
±5 mV
30 ppm/°C
dB
ms
AVDD
V
mV
µV/°C
1.2 mA
Bits
LSB
±1 LSB
mV
mV
±0.8 %
%
µs
dB
dB
dB
dB
10 µV/°C
10 µV/°C
mA
VREF/AVDD − V
0.1
V/µs
µs
nV-sec
mV
mV/°C
°C
V
V
%
V
512 sec
Test Conditions/Comments
0.47 µF from VREF to AGND
TA = 25°C
TA = 25°C
TA = 25°C
RL = 5 kΩ, CL = 100 pF
Buffered
Guaranteed monotonic
2.5 V internal reference
Measured at Code 0
% of full scale on DAC0
Buffered
Buffer on
1 LSB change at major carry (where maximum
number of bits simultaneously change in the
DACxDAT register)
MCU in power-down or standby mode before
measurement
Two selectable trip points
Of the selected nominal trip point voltage
Rev. A | Page 6 of 96

6 Page









ADUC7122 pdf, datenblatt
ADuC7122
Table 6. SPI Slave Mode Timing (SPICPH = 1)
Parameter
Description
tCSE
A
CSE to SCLOCK edge
AA
tSL SCLOCK low pulse width1
tSH SCLOCK high pulse width1
tDAV Data output valid after SCLOCK edge
tDSU Data input setup time before SCLOCK edge
tDHD Data input hold time after SCLOCK edge
tDF Data output fall time
tDR Data output rise time
tSR SCLOCK rise time
tSF SCLOCK fall time
tSFS
CSE high after SCLOCK edge
AA
Min
200
1 × tUCLK
2 × tUCLK
0
1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
Typ
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
5
5
5
5
CS
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MOSI
tCS
tSH
tDAV
tSL
tDF
MSB
tSR
tDR
BITS 6 TO 1
tSFS
tSF
LSB
MISO
MSB IN
BITS 6 TO 1
tDSU
tDHD
Figure 5. SPI Slave Mode Timing (SPICPH = 1)
LSB IN
Data Sheet
Max Unit
ns
ns
ns
25 ns
ns
ns
12.5 ns
12.5 ns
12.5 ns
12.5 ns
ns
Rev. A | Page 12 of 96

12 Page





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