ADC1413D105 Datasheet PDF - NXP Semiconductors
| Part Number | ADC1413D105 | |
| Description | Dual 14 bits ADC/ 65 80 105 or 125 Msps/ serial JESD204A interface | |
| Manufacturers | NXP Semiconductors | |
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ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps; serial JESD204A
interface
Rev. 02 — 4 June 2009
Objective data sheet
1. General description
The ADC1413D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1413D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V
source for analog and a 1.8 V source for the output driver, it has two serial outputs,
because of the two lanes of differential outputs, which are compliant with the JESD204A
standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily
configure the ADC. A set of IC configurations is also available via the binary level control
pins taken, which are used at power-up. The device also includes a programmable gain
amplifier with flexible input voltage range.
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1413D ideal for use in communications, imaging and
medical applications.
2. Features
I SNR, 73 dB
I Input bandwidth, 600 MHz
I SFDR, 90 dBc
I Power dissipation, 995 mW at 80 Msps
I Sample rate up to 125 Msps
I SPI interface
I Dual channel 14-bit pipelined ADC core I Duty cycle stabilizer
I 3.3 V, 1.8 V single supplies
I High IF capability
I Flexible input voltage range:
I Offset binary, 2’s complement, gray
1 V (p-p) to 2 V (p-p) with 6 dB
code
programmable fine gain
I 2 configurable serial outputs
I Power-down and Sleep modes
I Compliant with JESD204A serial
I HVQFN56 package
transmission standard
I INL ± 1 LSB; DNL ± 0.5 LSB
3. Applications
I Wireless and wired broadband communications
I Spectral analysis
I Portable instrumentation
I Ultrasound equipment
I Imaging systems
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NXP Semiconductors
ADC1413D065/0w8w0w.D/1ata0Sh5eet/41U.c2om5
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
ADC1413D065_080_105_125_2
Objective data sheet
Table 2. Pin description …continued
Symbol
Pin Type [1]
INBP
14 I
VDDA
15 P
VDDA
16 P
SCLK/DFS
17 I
SDIO/DCS
18 I/O
CSB
19 I
AGND
20 G
RESET
21 I
SCRAMBLER
22 I
CFG0
23 I/O
CFG1
24 I/O
CFG2
25 I/O
CFG3
26 I/O
VDDD
27 P
DGND
28 G
DGND
29 G
DGND
30 G
VDDD
31 P
CMLPB
32 O
CMLNB
33 O
VDDD
34 P
DGND
35 G
DGND
36 G
VDDD
37 P
CMLNA
38 O
CMLPA
39 O
VDDD
40 P
DGND
41 G
DGND
42 G
SYNCP
43 I
SYNCN
44 I
DGND
45 G
VDDD
46 P
SWING_0
47 I
SWING_1
48 I
PLL_LOCK
49 O
VDDA
50 P
AGND
51 G
AGND
52 G
VDDA
53 P
SENSE
54 I
VREF
55 I/O
VDDA
56 P
Description
channel B analog input
analog power supply 3.3 V
analog power supply 3.3 V
SPI clock / data format select
SPI data IO/duty cycle stabilizer
chip select bar
analog ground
JEDEC digital IP reset
scrambler enable /disable
JEDEC link configuration or OTRA
JEDEC link configuration or OTRB
JEDEC link configuration
JEDEC link configuration
digital power supply 1.8 V
digital ground
digital ground
digital ground
digital power supply 1.8 V
channel B output
channel B complementary output
digital power supply 1.8 V
digital ground
digital ground
digital power supply 1.8 V
channel A complementary output
channel A output
digital power supply 1.8 V
digital ground
digital ground
synchronization from FPGA
synchronization from FPGA
digital ground
digital power supply 1.8 V
JESD204 serial buffer programmable output swing
JESD204 serial buffer programmable output swing
set when internal PLL is locked
analog power supply 3.3 V
analog ground
analog ground
analog power supply 3.3 V
reference programming pin
voltage reference input/output
analog power supply 3.3 V
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
Rev. 02 — 4 June 2009
© NXP B.V. 2009. All rights reserved.
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