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ADC1413D080 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer ADC1413D080
Beschreibung Dual 14 bits ADC/ 65 80 105 or 125 Msps/ serial JESD204A interface
Hersteller NXP Semiconductors
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Gesamt 30 Seiten
ADC1413D080 Datasheet, Funktion
www.DataSheet4U.com
ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps; serial JESD204A
interface
Rev. 02 — 4 June 2009
Objective data sheet
1. General description
The ADC1413D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1413D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V
source for analog and a 1.8 V source for the output driver, it has two serial outputs,
because of the two lanes of differential outputs, which are compliant with the JESD204A
standard. An integrated SPI (Serial Peripheral Interface) allows the user to easily
configure the ADC. A set of IC configurations is also available via the binary level control
pins taken, which are used at power-up. The device also includes a programmable gain
amplifier with flexible input voltage range.
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1413D ideal for use in communications, imaging and
medical applications.
2. Features
I SNR, 73 dB
I Input bandwidth, 600 MHz
I SFDR, 90 dBc
I Power dissipation, 995 mW at 80 Msps
I Sample rate up to 125 Msps
I SPI interface
I Dual channel 14-bit pipelined ADC core I Duty cycle stabilizer
I 3.3 V, 1.8 V single supplies
I High IF capability
I Flexible input voltage range:
I Offset binary, 2’s complement, gray
1 V (p-p) to 2 V (p-p) with 6 dB
code
programmable fine gain
I 2 configurable serial outputs
I Power-down and Sleep modes
I Compliant with JESD204A serial
I HVQFN56 package
transmission standard
I INL ± 1 LSB; DNL ± 0.5 LSB
3. Applications
I Wireless and wired broadband communications
I Spectral analysis
I Portable instrumentation
I Ultrasound equipment
I Imaging systems






ADC1413D080 Datasheet, Funktion
NXP Semiconductors
ADC1413D065/0w8w0w.D/1ata0Sh5eet/41U.c2om5
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
7. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VDDA
VDDD
VCC
Tstg
Tamb
analog supply voltage
digital supply voltage
supply voltage difference
storage temperature
ambient temperature
VDDA VDDD
[1] 2.85
[2] 1.65
<tbd>
55
40
Tj junction temperature
-
Max
3.6
1.95
<tbd>
+125
+85
125
Unit
V
V
V
°C
°C
°C
[1] The supply voltage VDDA may have any value between 0.5 V and +7.0 V provided that the supply voltage
differences VCC are respected.
[2] The supply voltage VDDD may have any value between 0.5 V and +5.0 V provided that the supply voltage
differences VCC are respected.
8. Thermal characteristics
Table 4.
Symbol
Rth(j-a)
Rth(j-c)
Thermal characteristics
Parameter
Conditions Typ
thermal resistance from junction to ambient
[1] 20.9[2]
thermal resistance from junction to case
[1] <tbd>
[1] In compliance with JEDEC test board, in free air.
[2] Value for 4 layers and 36 vias.
Unit
K/W
K/W
9. Static characteristics
Table 5. Characteristics
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = 40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V;
Vi (INAP, INBP) Vi (INAM, INBM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Unit
Supplies
VDDA
VDDD
IDDA
IDDD
Ptot
analog supply voltage
digital supply voltage
analog supply current
digital supply current
total power dissipation
fclk = 125 Msample/s;
fi =70 MHz
fclk = 125 Msample/s;
fi = 70 MHz
fclk = 125 Msample/s
fclk = 105 Msample/s
fclk = 80 Msample/s
fclk = 65 Msample/s
2.85
1.65
-
-
-
-
-
-
3.0
1.8
343
150
1270
1150
995
885
3.4
3.6
-
-
-
-
-
-
V
V
mA
mA
mW
mW
mW
mW
ADC1413D065_080_105_125_2
Objective data sheet
Rev. 02 — 4 June 2009
© NXP B.V. 2009. All rights reserved.
6 of 38

6 Page









ADC1413D080 pdf, datenblatt
NXP Semiconductors
ADC1413D065/0w8w0w.D/1ata0Sh5eet/41U.c2om5
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 8. Characteristics …continued
Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C and CL = 5 pF.
Min. and max. values are across the full temperature range Tamb = 40 °C to +85 °C at VDDA = 3 V, VDDD = 1.8 V;
Vi (INAP, INBP) Vi (INAM, INBM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless
otherwise specified.
Symbol
Parameter Conditions
Min Typ Max Unit
tw(SCLKL)
SCLK pulse
width LOW
16
ns
tsu set-up time data to
SCLKH
5
ns
CSB to
SCLKH
th
hold time
data to
SCLKH
2
ns
CSB to
SCLKH
2
ns
fclk(max)
maximum
clock
frequency
25 MHz
13. Application information
13.1 Analog inputs
13.1.1 Input stage description
The ADC1413D inputs can be configured as single-ended or differential (selected via SPI
control bit DIFF/SE; see Table 20). Optimal performance is achieved using differential
inputs with the common-mode input voltage, VI(cm), set to VDDA/2.
The full scale analog input voltage range is configurable between ± 1 V (p-p) and
± 2 V (p-p) via a programmable internal reference (see Section 13.2 and Table 21 for
further details).
The equivalent circuit of the sample and hold input stage, including ESD protection and
circuit and package parasitics, is shown in Figure 5.
ADC1413D065_080_105_125_2
Objective data sheet
Rev. 02 — 4 June 2009
© NXP B.V. 2009. All rights reserved.
12 of 38

12 Page





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