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PDF AD9269 Data sheet ( Hoja de datos )
| Número de pieza | AD9269 | |
| Descripción | 1.8 V Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
16-Bit, 20/40/65/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9269
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.5/+1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND
SDIO SCLK CSB
VIN+A
VIN–A
AD9269
SPI
ADC
PROGRAMMING DATA
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
QUADRATURE
ERROR
CORRECTION
ADC
DIVIDE DUTY CYCLE
1 TO 6 STABILIZER
MODE
CONTROLS
ORA
D15A
D0A
DCOA
DRVDD
ORB
D15B
D0B
DCOB
CLK+ CLK–
SYNC
DCS
Figure 1.
PDWN DFS OEB
PRODUCT HIGHLIGHTS
1. The AD9269 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. An optional SPI selectable dc correction and quadrature
error correction (QEC) feature corrects for dc offset, gain,
and phase mismatches between the two channels.
4. A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing
and offset adjustments, and voltage reference modes.
5. The AD9269 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC
the AD9231 12-bit ADC, the AD6659 12-bit baseband
diversity receiver, and the AD9204 10-bit ADC, enabling a
simple migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9269
Parameter
POWER
CONSUMPTION
DC Input
Sine Wave Input2
(DRVDD = 1.8 V)
Sine Wave Input2
(DRVDD = 3.3 V)
Standby Power4
Power-Down Power
Temp
Full
Full
Full
Full
Full
AD9269-20/AD9269-40
Min Typ
Max
87.7/121.7
96.9/136.3 102.0/142.3
114.4/165.7
37/37
1.0
Min
AD9269-65
Typ Max
170.7
191.2
235.6
37
1.0
199.8
AD9269-80
Min Typ
Max
200
224.6
279
37
1.0
240
1 Measured with a 1.0 V external reference.
2 Measured with a 10 MHz input frequency at a rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4 Standby power is measured with a dc input and the CLK+, CLK− active.
Unit
mW
mW
mW
mW
mW
Rev. A | Page 5 of 40
5 Page 
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK+ 1
CLK– 2
SYNC 3
D0B (LSB) 4
D1B 5
D2B 6
D3B 7
D4B 8
D5B 9
DRVDD 10
D6B 11
D7B 12
D8B 13
D9B 14
D10B 15
D11B 16
PIN 1
INDICATOR
AD9269
TOP VIEW
(Not to Scale)
48 PDWN
47 OEB
46 CSB
45 SCLK/DFS
44 SDIO/DCS
43 ORA
42 D15A (MSB)
41 D14A
40 D13A
39 D12A
38 D11A
37 DRVDD
36 D10A
35 D9A
34 D8A
33 D7A
AD9269
NOTES
1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description
0, EP
AGND
The exposed paddle is the only ground connection. It must be soldered to the PCB analog ground to
ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.
1, 2 CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
3
SYNC
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
4 to 9, 11 to
18, 20, 21
D0B (LSB) to Channel B Digital Outputs. D0B is the LSB; D15B is the MSB.
D15B (MSB)
10, 19, 28, 37 DRVDD
Digital Output Driver Supply (1.8 V to 3.3 V).
22 ORB Channel B Out-of-Range Digital Output.
23
DCOB
Channel B Data Clock Digital Output.
24
DCOA
Channel A Data Clock Digital Output.
25 to 27, 29 to D0A (LSB) to Channel A Digital Outputs. D0A is the LSB; D15A is the MSB.
36, 38 to 42 D15A (MSB)
43 ORA Channel A Out-of-Range Digital Output.
44
SDIO/DCS
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal
pull-up in non-SPI (DCS) mode.
45
SCLK/DFS
SPI Clock (SCLK). Input in SPI mode. 30 kΩ internal pull-down.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down.
DFS high: twos complement output.
DFS low: offset binary output.
46 CSB SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
47 OEB Digital Input. 30 kΩ internal pull-down.
Low: enable Channel A and Channel B digital outputs.
High: three-state outputs.
48
PDWN
Digital Input. 30 kΩ internal pull-down.
High: power down device.
Low: run device, normal operation.
Rev. A | Page 11 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9269.PDF ] | |
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