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PDF AD7195 Data sheet ( Hoja de datos )
| Número de pieza | AD7195 | |
| Descripción | 24-BIT SIGMA-DELTA ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7195 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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4.8 kHz, UltralowwwwN.DoatiasSheee,t42U.4co-mBit
Sigma-Delta ADC with PGA and AC Excitation
AD7195
FEATURES
AC or DC sensor excitation
RMS noise: 8.5 nV at 4.7 Hz (gain = 128)
16 noise-free bits at 2.4 kHz (gain = 128)
Up to 22.5 noise-free bits (gain = 1)
Offset drift: 5 nV/°C
Gain drift: 1 ppm/°C
Specified drift over time
2 differential/4 pseudo differential input channels
Automatic channel sequencer
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
Power supply
AVDD: 4.75 V to 5.25 V
DVDD: 2.7 V to 5.25 V
Current: 6 mA
Temperature range: –40°C to +105°C
Package: 32-lead LFCSP
INTERFACE
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Chromatography
PLC/DCS analog input modules
Data acquisition
Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7195 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can be interfaced directly to the ADC. The AD7195
contains ac excitation, which is used to remove dc-induced
offsets from bridge sensors.
The device can be configured to have two differential inputs or
four pseudo differential inputs. The on-chip channel sequencer
allows several channels to be enabled, and the AD7195 sequentially
converts on each enabled channel. This simplifies communication
with the part. The on-chip 4.92 MHz clock can be used as the
clock source to the ADC or, alternatively, an external clock or
crystal can be used. The output data rate from the part can be
varied from 4.7 Hz to 4.8 kHz.
The device has two digital filter options. The choice of filter
affects the rms noise/noise-free resolution at the programmed
output data rate, the settling time, and the 50 Hz/60 Hz rejec-
tion. For applications that require all conversions to be settled,
the AD7195 includes a zero latency feature.
Weigh scales
Strain gage transducers
Pressure measurement
Temperature measurement
The part operates with a 5 V analog power supply and a digital
power supply from 2.7 V to 5.25 V. It consumes a current of
6 mA. It is housed in a 32-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND
REFIN(+) REFIN(–)
AIN1
AIN2
AIN3
AIN4
AINCOM
BPDSW
AVDD
MUX
PGA
Σ-Δ
ADC
AGND
TEMP
SENSOR
AD7195
AC
EXCITATION
CLOCK
REFERENCE
DETECT
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
SYNC
CLOCK
CIRCUITRY
ACX1 ACX1
Figure 1.
ACX2
ACX2 MCLK1 MCLK2
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
AD7195www.DataSheet4U.com
Parameter
LOGIC INPUTS
Input High Voltage, VINH2
Input Low Voltage, VINL2
Hysteresis2
Input Currents
LOGIC OUTPUT (DOUT/RDY)
Output High Voltage, VOH2
Output Low Voltage, VOL2
Output High Voltage, VOH2
Output Low Voltage, VOL2
Floating-State Leakage
Current
Floating-State Output
Capacitance
Data Output Coding
SYSTEM CALIBRATION2
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
Input Span
POWER REQUIREMENTS7
Power Supply Voltage
AVDD − AGND
DVDD − DGND
Power Supply Currents
AIDD Current
DIDD Current
IDD (Power-Down Mode)
Min
2
0.1
−10
DVDD − 0.6
4
−10
−1.05 × FS
0.8 × FS
4.75
2.7
Typ Max
0.8
0.25
+10
0.4
0.4
+10
10
Offset binary
1.05 × FS
2.1 × FS
5.25
5.25
0.85 1
1.1 1.3
3.5 4.5
45
5 6.4
5.5 6.9
0.35 0.4
0.5 0.6
1.5
2
Unit
V
V
V
μA
V
V
V
V
μA
pF
Test Conditions/Comments1
DVDD = 3 V, ISOURCE = 100 μA
DVDD = 3 V, ISINK = 100 μA
DVDD = 5 V, ISOURCE = 200 μA
DVDD = 5 V, ISINK = 1.6 mA
V
V
V
V
V
mA gain = 1, buffer off
mA gain = 1, buffer on
mA gain = 8, buffer off
mA gain = 8, buffer on
mA gain = 16 to 128, buffer off
mA gain = 16 to 128, buffer on
mA DVDD = 3 V
mA DVDD = 5 V
mA External crystal used
μA
1 Temperature range: −40°C to +105°C.
2 Specification is not production tested, but is supported by characterization data at initial product release.
3 FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register.
4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
5 The analog inputs are configured for differential mode.
6 REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection.
7 Digital inputs equal to DVDD or DGND.
Rev. 0 | Page 5 of 44
5 Page 
TYPICAL PERFORMANCE CHARACTERISTICS
8,388,760
8,388,758
8,388,756
8,388,754
8,388,752
8,388,750
8,388,748
8,388,746
0
200 400 600 800 1000
SAMPLE
Figure 6. Noise (VREF = 5 V, Output Data Rate = 4.7 Hz, Gain = 128,
Chop Disabled, Sinc4 Filter)
250
200
150
100
50
0
CODE
Figure 7. Noise Distribution Histogram (VREF = 5 V,
Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)
8,388,950
8,388,900
8,388,850
8,388,800
8,388,750
8,388,700
8,388,650
8,388,600
8,388,550
8,388,500
8,388,450
0
100 200 300 400 500 600 700 800 900 1000
SAMPLES
Figure 8. Noise (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 128,
Chop Disabled, Sinc4 Filter)
AD7195www.DataSheet4U.com
30
25
20
15
10
5
0
8,388,490
8,388,576
8,388,662 8,388,748
CODE
8,388,834
8,388,920
Figure 9. Noise Distribution Histogram (VREF = 5 V,
Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc4 Filter)
8,388,820
8,388,800
8,388,780
8,388,760
8,388,740
8,388,720
8,388,700
8,388,680
8,388,660
8,388,640
8,388,620
0
100 200 300 400 500 600 700 800 900 1000
SAMPLES
Figure 10. Noise (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 1,
Chop Disabled, Sinc4 Filter)
80
70
60
50
40
30
20
10
0
8,388,620
8,388,660
8,388,700 8,388,740
CODE
8,388,780
8,388,820
Figure 11. Noise Distribution Histogram (VREF = 5 V,
Output Data Rate = 4800 Hz, Gain = 1, Chop Disabled, Sinc4 Filter)
Rev. 0 | Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7195.PDF ] | |
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