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PDF 89LPC901FN Data sheet ( Hoja de datos )
| Número de pieza | 89LPC901FN | |
| Descripción | P89LPC901FN | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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P89LPC901/902/903 www.DataSheet4U.com
8-bit microcontrollers with two-clock 80C51 core
1 kB 3 V Flash with 128-byte RAM
Rev. 04 — 21 November 2003
Product data
1. General description
The P89LPC901/902/903 are single-chip microcontrollers in low-cost 8-pin packages,
based on a high performance processor architecture that executes instructions in two
to four clocks, six times the rate of standard 80C51 devices. Many system-level
functions have been incorporated into the P89LPC901/902/903 in order to reduce
component count, board space, and system cost.
2. Features
2.1 Principal features
s 1 kB byte-erasable Flash code memory organized into 256-byte sectors and
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile
data storage.
s 128-byte RAM data memory.
s Two 16-bit counter/timers. (P89LPC901 Timer 0 may be configured to toggle a
port output upon timer overflow or to become a PWM output.)
s 23-bit system timer that can also be used as a Real-Time clock.
s Two analog comparators (P89LPC902 and P89LPC903, single analog
comparator on P89LPC901).
s Enhanced UART with fractional baudrate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities
(P89LPC903).
s High-accuracy internal RC oscillator option allows operation without external
oscillator components. The RC oscillator option is selectable and fine tunable.
s 2.4 V to 3.6 V VDD operating range with 5 V tolerant I/O pins (may be pulled up or
driven to 5.5 V). Industry-standard pinout with VDD, VSS, and reset at locations 1,
8, and 4.
s Up to six I/O pins when using internal oscillator and reset options.
s 8-pin SO-8 package.
2.2 Additional features
s A high performance 80C51 CPU provides instruction cycle times of 167 ns to
333 ns for all instructions except multiply and divide when executing at 12 MHz.
This is six times the performance of the standard 80C51 running at the same
clock frequency. A lower clock frequency for the same performance results in
power savings and reduced EMI.
s In-Application Programming (IAP-Lite) and byte erase allows code memory to be
used for non-volatile data storage.
1 page  
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with twwwow-c.DloactakSh8e0eCt45U1.ccoomre
P89LPC902
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
1 kB
CODE FLASH
128-BYTE
DATA RAM
PORT 1
INPUT
INTERNAL
BUS
PORT 0
CONFIGURABLE I/Os
TIMER 0
TIMER 1
REAL-TIME CLOCK/
SYSTEM TIMER
ANALOG
COMPARATORS
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
PROGRAMMABLE
OSCILLATOR DIVIDER
ON-CHIP
RC
OSCILLATOR
CPU
CLOCK
Fig 2. P89LPC902 block diagram.
002aaa445
9397 750 12293
Product data
Rev. 04 — 21 November 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5 of 55
5 Page 
Philips Semiconductors
P89LPC901/902/903
8-bit microcontrollers with twwwow-c.DloactakSh8e0eCt45U1.ccoomre
Table 5: P89LPC903 pin description
Symbol
Pin
Type Description
P0.0 - P0.6 2, 6, 7 I/O Port 0: Port 0 is an I/O port with a user-configurable output type. During reset Port 0
latches are configured in the input only mode with the internal pull-up disabled. The
operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 8.12.1 “Port
configurations” and Table 13 “DC electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
2 I/O P0.2 — Port 0 bit 2.
I CIN2A — Comparator 2 positive input.
I KBI2 — Keyboard input 2.
7 I/O P0.4 — Port 0 bit 4.
I CIN1A — Comparator 1 positive input.
I KBI4 — Keyboard input 4.
6 I/O P0.5 — Port 0 bit 5.
I CMPREF — Comparator reference (negative) input.
I KBI5 — Keyboard input 5.
P1.0 - P1.5 3, 4, 5
Port 1: Port 1 is an I/O port with a user-configurable output type. During reset Port 1
latches are configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends upon the
port configuration selected. Each of the configurable port pins are programmed
independently. Refer to Section 8.12.1 “Port configurations” and Table 13 “DC
electrical characteristics” for details. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
5 I/O P1.0 — Port 1 bit 0.
O TxD — Serial port transmitter data.
3 I/O P1.1 — Port 1 bit 1.
I RxD — Serial port receiver data.
4 I P1.5 — Port 1 bit 5 (input only).
I RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode.
VSS 8 I Ground: 0 V reference.
VDD 1 I Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
9397 750 12293
Product data
Rev. 04 — 21 November 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
11 of 55
11 Page | ||
| Páginas | Total 55 Páginas | |
| PDF Descargar | [ Datasheet 89LPC901FN.PDF ] | |
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